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AL1214H PDF预览

AL1214H

更新时间: 2022-01-19 05:40:00
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13页 176K
描述
AL1214H 10Bit 80MSPS DAC|Data Sheet

AL1214H 数据手册

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10BIT 80MSPS DAC  
FUNCTIONAL DESCRIPTION  
AL1214H  
This is  
a 10bit 80MSPS digital to analog data  
Linearity Error : Linearity error is defined as the  
maximum deviation of the actual analog output from  
the ideal output, determined by a straight line drawn  
from zero to full scale.  
converter and uses segment architecture for 5bits of  
MSB sides and binary-weighted architecture for 5bits  
of LSB side. It contains of 1'st latch block, decoder  
block, 2nd latch block, AMP block, CM (current  
mirror ) block and analog switch block. This core  
uses reference current to decide the 1LSB current size  
by dividing the reference current by 116 times. So the  
reference current must be constant and the switch's  
physical real size can be constant by using AMP  
block with high DC gain. The most significant block  
of this core is analog switch block and it must  
maintain the uniformity at each switch, so layout  
designer must care of the matching characteristics on  
analog switch and CM block. And more than 80%  
of supply current is dissipated at analog switch block  
and AMP block. And it uses samsung(SEC) standard  
cell as all digital cell of latch , decoder and buffer.  
And to adjust full current output, you must decide the  
"Rset" resistor value(connected to IREF pin) .Its  
voltage output can be obtained by connecting Rload  
(connected to IO pin) .  
Monotonicity  
:
A D/A converter is monotonic if  
the output either increases or remains constants as  
the digital input increases.  
Offset Error : The deviation of the output current  
from the ideal of zero is called offset error. For IO ,  
0mV output expected when the inputs are all 0s.  
Gain Errors  
:
The difference between the actual  
andideal output span. The actual span is determined  
by the output when all inputs are set to 1s minus the  
output when all inputs are set to 0s.  
Output Compliance Range : The range of allowable  
voltage at the output of a current-output DAC.  
Operation beyond the maximum compliance limits may  
cause either output stage saturation or breakdown  
resulting in nonlinear performance.  
Settling Time : The time required for the output to  
reach and remain within a specified error band about  
its final value, measured from the start of the output  
transition  
Glitch Impulse : Asymmetrical switching times in a  
DAC give rise to undesired output transients that are  
quantified by a glitch impulse. It is specified as the  
net area of the glitch in pV-s  
SEC ASIC  
ANALOG  
5 / 12  

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