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AK8181E PDF预览

AK8181E

更新时间: 2024-01-08 20:27:24
品牌 Logo 应用领域
AKM 时钟
页数 文件大小 规格书
10页 552K
描述
3.3V LVPECL 1:4 Clock Fanout Buffer

AK8181E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LQFP, QFP32,.35SQ,32Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.75
系列:8181输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G32长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.375/3.8 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.8 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:700 MHzBase Number Matches:1

AK8181E 数据手册

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AK8181E  
3.3V LVPECL 1:4  
Preliminary Clock Fanout Buffer  
AK8181E  
Features  
Description  
The AK8181E is a member of AKMs LVPECL  
clock fanout buffer family designed for telecom,  
networking and computer applications, requiring a  
range of clocks with high performance and low  
skew. The AK8181E distributes 4 buffered clocks.  
Four differential 3.3V LVPECL outputs  
Selectable crystal or differential clock inputs  
Clock output frequency up to 650MHz  
Translates any single-ended input signal to  
3.3V LVPECL levels with resistor bias on  
PCLKn input  
AK8181E are derived from AKMs long-term-  
experienced clock device technology, and enable  
clock output to perform low skew. The AK8181E is  
available in a 20-pin TSSOP package.  
Output skew : 10ps (typical)  
Part-to-part skew : 150ps (maximum)  
Propagation delay : 0.9ns (typical)  
Additive phase jitter(RMS):  
PCLKp/n@156.25MHz : 0.04ps (typical)  
XTAL@50MHz  
: 0.14ps (typical)  
Operating Temperature Range: -40 to +85  
Package: 20-pin TSSOP (Pb free)  
Pin compatible with ICS8533I-31  
Block Diagram  
draft-E-01  
Feb-2013  
- 1 -  

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