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AK5574EN PDF预览

AK5574EN

更新时间： 2022-02-26 13:47:54

品牌	Logo	应用领域
AKM		/
页数	文件大小	规格书
68页	2036K
描述
4-Channel Differential 32-bit ÎÎ£ ADC

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数据手册

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AK5574EN 数据手册

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[AK5574]

■ Pin Functions

Power Down

Status

No. Pin Name

I/O Function

1

2

3

4

5

6

7

8

9

NC

-

I

I

I

I

-

-

I

I

I

I

-

I

I

I

I

NC Pin (The pins that are not to be connected)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VREFL1

VREFH1

AIN2N

AIN2P

AVDD

AVSS

AIN3P

AIN3N

ADC Low Level Voltage Reference Input Pin

ADC High Level Voltage Reference Input Pin

Channel 2 Negative Input Pin

Channel 2 Positive Input Pin

Analog Power Supply Pin (AIN1-4), 4.75-5.25 V

Analog Ground Pin (AIN1-4)

Channel 3 Positive Input Pin

Channel 3 Negative Input Pin

ADC High Level Voltage Reference Input Pin

ADC Low Level Voltage Reference Input Pin

NC Pin (The pins that are not to be connected)

Channel 4 Negative Input Pin

10 VREFH2

11 VREFL2

12 NC

13 AIN4N

14 AIN4P

15 TEST

16 MCLK

Channel 4 Positive Input Pin

TEST Enable Pin

Master Clock Input Pin

Digital I/O Buffers and LDO Power Supply Pin,

1.7-1.98 V (LDOE pin= “L”) or 3.0-3.6 V (LDOE pin= “H”).

Digital Ground Pin

17 TVDD

18 DVSS

-

-

-

I

-

-

Digital Core Power Supply Pin, 1.7-1.98V (LDOE pin= “L”)

Hi-z & Pull

Down with

500 Ω

-

19 VDD18

O

LDO Stabilization Capacitor Connect Pin. (LDOE pin= “H”)

Reset & Power Down Pin

“L”: Reset & Power Down, “H” : Normal Operation

20 PDN

I

21 PW0

22 PW1

23 PW2

24 MSN

I

I

I

I

Power Management Pin, Channel Summation Select Pin1

Power Management Pin, Channel Summation Select Pin2

Power Management Pin, Channel Summation Select Pin3,

Master/Slave Select Pin

-

-

-

-

Audio Serial Data Clock Input Pin in PCM & Slave Mode

(This pin is pull down by 100 kΩ internally.)

Audio Serial Data Clock Output Pin in PCM & Master Mode

(This pin is pull down by 100 kΩ internally.)

DSD Clock Output Pin in DSD Mode

(This pin is pull down by 100 kΩ internally.)

Channel Clock Input Pin in PCM & Slave Mode

(This pin is pull down by 100 kΩ internally.)

Channel Clock Output Pin in PCM & Master Mode

(This pin is pull down by 100 kΩ internally.)

Audio Serial Data Output Pin for AIN1 in DSD Mode

(This pin is pull down by 100 kΩ internally.)

TDM Data Input Pin in PCM Mode

(This pin is pull down by 100 kΩ internally.)

Audio Serial Data Output Pin for AIN2 in DSD Mode

(This pin is pull down by 100 kΩ internally.)

Audio Serial Data Output Pin for AIN1 and AIN2 in PCM Mode

Audio Serial Data Output Pin for AIN3 in DSD Mode

Audio Serial Data Output Pin for AIN3 and AIN4 in PCM Mode

Audio Serial Data Output Pin for AIN4 in DSD Mode

I

-

BICK

25

O

O

I

Hi-z

Hi-z

-

DCLK

LRCK

26

O

O

I

Hi-z

Hi-z

-

DSDOL1

TDMIN

27

DSDOR1

O

Hi-z

SDTO1

28

O

O

O

O

L

L

L

L

DSDOL2

SDTO2

DSDOR2

29

30 OVF

O

Analog Input Over Flow Flag Output Pin

L

015016764-E-00

2015/12

- 5 -

1 2 3 456 7 8...68

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