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AK2048D

更新时间： 2024-02-08 02:23:56

品牌	Logo	应用领域
AKM		/
页数	文件大小	规格书
16页	89K
描述
2M CMI Transceiver

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技术参数
数据手册

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AK2048D 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP, QFP44,.7SQ,40	针数：	44
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	JESD-30 代码：	S-PQFP-G44
长度：	14 mm	功能数量：	1
端子数量：	44	最高工作温度：	80 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP44,.7SQ,40
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	5 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	COMMERCIAL EXTENDED
端子形式：	GULL WING	端子节距：	1 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

AK2048D 数据手册

ASAHI KASEI

[AK2048]

PIN DESCRIPTIONS

Pin Name

I/O

Function

Receive Data output recovered from the incoming data. Delay time from the incoming

data to the RDATA is about 1.25bit. Output on the rising edge of RCLK.

Receive Clock Output recovered from the incoming data.

RDATA

RCLK

RCRV

CRV (Code Rule Violation) output pin.

When AK2048D detects the CRV of CMI codes from in the coming data, RCRV goes

to “high” synchronized with the violation data. CRV is detected for both “0” data and

“1” data. Refer to Fig.6, 11

Transmit Data Input pin.

TDATA

Input on the falling edge of TCLK.

Transmit Clock Input pin.

TCLK

TCRV

If this input is “high”, AK2048D generates CRV in the transmit data.

CRV is generated for both “0”data and “1”data. “High” input TCRV is accepted until 5

clocks duration. If the duration of “High” input is longer than 6 clocks, TCRV input

after 6th clock is ignored. Refer to Fig.4, 11

Test pin. Should be floated.

TEST1

TEST2

LOCK

Test pin. Should be floated.

LOCK indicates the PLL status whether PLL is in the LOCK status or PLL is in the

UNLOCK status.

LOCK status

LOCK becomes “Low” when the sampled RCLK are all “Low” during the consecutive

32 RXA-RXB sample clock duration.

UN LOCK status

LOCK becomes “High” when the following both conditions are satisfied.

- The sampled RCLK are “High” more than 5 clocks in the frame of the consecutive

256 RXA-RXB clock duration.

- And the above happens in the 5 consecutive frames.

In another condition, LOCK keeps the current output status without change.

The output timing of this signal is asynchronous with RCLK.

When RST is “Low”, LOCK is fixed to “High”.

MS0073-E-00

2001/01

1 2 345 6 7...16

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