Datasheet > AGLP125-V2VQG289ES

AGLP125-V2VQG289ES

更新时间： 2025-08-09 08:21:59

品牌	Logo	应用领域
ACTEL		闪存
页数	文件大小	规格书
14页	517K
描述
IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology

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数据手册

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v1.3

IGLOO PLUS Low-Power Flash FPGAs

with Flash*Freeze Technology

High-Performance Routing Hierarchy

Features and Benefits

A^•dv^Sa^egn^mce^end^teI^d/O^{, Hierarchical Routing and Clock Structure}

Low Power

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—4 Banks per Chip on All

IGLOO PLUS Devices

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Configurable Hold Previous State, Tristate, HIGH, or LOW

State per I/O in Flash*Freeze Mode

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

• Selectable Schmitt Trigger Inputs

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

Feature Rich

• 30 k to 125 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 212 User I/Os

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Small-Footprint Packages across the IGLOO

PLUS Family

Clock Conditioning Circuit (CCC) and PLL^†

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Six CCC Blocks, One with an Integrated PLL

• Configurable

Phase

Shift, Multiply/Divide,

Delay

Capabilities, and External Feedback

• Retains Programmed Design When Powered Off

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

In-System Programming (ISP) and Security

Embedded Memory

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• 1 kbit of FlashROM User Nonvolatile Memory

†

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

†

• FlashLock to Secure FPGA Contents

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18)

Table 1-1 • IGLOO PLUS Product Family

IGLOO PLUS Devices

AGLP030

AGLP060

60 k

512

1,584

AGLP125

125 k

1,024

3,120

System Gates

30 k

256

792

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

–

Secure (AES) ISP

–

Yes

1 k

Yes

1 k

FlashROM Bits

1 k

–

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

120

157

212

Package Pins

CS201, CS289

VQ128

CS201, CS289

VQ176

CS281, CS289

Notes:

1. AGLP060 in CS201 does not support the PLL.

2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.

†

The AGLP030 device does not support this feature.

December 2008

12 3 4 5 6 7...14

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与AGLP125-V2VQG289ES相关器件

型号	品牌	获取价格	描述	数据表
AGLP125-V2VQG289I	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V2VQG289PP	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V5CS289	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V5CS289ES	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V5CS289I	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V5CS289PP	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V5CSG289	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V5CSG289ES	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V5CSG289I	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125-V5CSG289PP	ACTEL	获取价格	IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology

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