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AFL12005DW/ES PDF预览

AFL12005DW/ES

更新时间: 2024-02-24 09:41:52
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
11页 183K
描述
DC-DC Regulated Power Supply Module, 2 Output, 80W, Hybrid, 0.380 INCH, LOW PROFILE, SEAM WELDED PACKAGE-12

AFL12005DW/ES 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:0.380 INCH, LOW PROFILE, SEAM WELDED PACKAGE-12Reach Compliance Code:compliant
风险等级:5.18其他特性:ADDITIONAL -5V OUTPUT AVAILABLE
模拟集成电路 - 其他类型:DC-DC REGULATED POWER SUPPLY MODULE最大输入电压:160 V
最小输入电压:80 V标称输入电压:120 V
JESD-30 代码:R-XDMA-P12JESD-609代码:e0
最大负载调整率:1%功能数量:1
输出次数:2端子数量:12
最高工作温度:125 °C最低工作温度:-55 °C
最大输出电流:12.8 A最大输出电压:5.5 V
最小输出电压:4.583 V标称输出电压:5 V
封装主体材料:UNSPECIFIED封装等效代码:MODULE,12LEAD,2.5
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
子类别:Other Analog ICs表面贴装:NO
技术:HYBRID温度等级:MILITARY
端子面层:TIN LEAD端子形式:PIN/PEG
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大总功率输出:80 W微调/可调输出:YES
Base Number Matches:1

AFL12005DW/ES 数据手册

 浏览型号AFL12005DW/ES的Datasheet PDF文件第2页浏览型号AFL12005DW/ES的Datasheet PDF文件第3页浏览型号AFL12005DW/ES的Datasheet PDF文件第4页浏览型号AFL12005DW/ES的Datasheet PDF文件第6页浏览型号AFL12005DW/ES的Datasheet PDF文件第7页浏览型号AFL12005DW/ES的Datasheet PDF文件第8页 
AFL120XXD Series  
Block Diagram  
Figure I. AFL Dual Output  
INPUT  
FILTER  
1
4
+ INPUT  
OUTPUT  
FILTER  
+ OUTPUT  
7
8
9
PRIMARY  
BIAS SUPPLY  
CURRENT  
SENSE  
ENABLE 1  
OUTPUT RETURN  
- OUTPUT  
OUTPUT  
FILTER  
5
SYNC OUTPUT  
SHARE  
11  
12  
10  
CONTROL  
SHARE  
AMPLIFIER  
ERROR  
AMP  
& REF  
6
3
2
SYNC INPUT  
CASE  
FB  
ENABLE 2  
OUTPUT  
VOLTAGE TRIM  
INPUT RETURN  
Although incorporating several sophisticated and useful  
ancilliary features, basic operation of the AFL120XXDseries  
can be initiated by simply applying an input voltage to pins 1  
and 2 and connecting the appropriate loads between pins 7,  
8, and 9. Of course, operation of any converter with high  
power density should not be attempted before secure  
attachment to an appropriate heat dissipator. (See Thermal  
Considerations, page 7)  
Circuit Operation and Application Information  
The AFL series of converters employ a forward switched  
mode converter topology. (refer to Figure I.) Operation of  
the device is initiated when a DC voltage whose magnitude  
is within the specified input limits is applied between pins 1  
and 2. If pins 4 and 12 are enabled (at a logical 1 or open)  
the primary bias supply will begin generating a regulated  
housekeeping voltage bringing the circuitry on the primary  
side of the converter to life. Two power MOSFETs used to Inhibiting Converter Output (Enable)  
chop the DC input voltage into a high frequency square  
As an alternative to application and removal of the DC voltage  
wave, apply this chopped voltage to the power transformer.  
to the input, the user can control the converter output by  
As this switching is initiated, a voltage is impressed on a  
providing TTL compatible, positive logic signals to either of  
second winding of the power transformer which is then  
two enable pins (pin 4 or 12). The distinction between these  
rectified and applied to the primary bias supply. When this  
two signal ports is that enable 1 (pin 4) is referenced to the  
occurs, the input voltage is excluded from the bias voltage  
input return (pin 2) while enable 2 (pin 12) is referenced to  
generator and the primary bias voltage becomes internally  
the output return (pin 8). Thus, the user has access to an  
generated.  
inhibit function on either side of the isolation barrier. Each  
port is internally pulled “high” so that when not used, an  
The switched voltage impressed on the secondary output  
open connection on both enable pins permits normal  
transformer windings is rectified and filtered to provide the  
converter operation. When their use is desired, a logical  
positive and negative converter output voltages. An error  
“low” on either port will shut the converter down.  
amplifier on the secondary side compares the positive output  
voltage to a precision reference and generates an error  
signal proportional to the difference. This error signal is  
Figure II. Enable Input Equivalent Circuit  
+5.6V  
magnetically coupled through the feedback transformer into  
the control section of the converter varying the pulse width  
of the square wave signal driving the MOSFETs, narrowing  
the pulse width if the output voltage is too high and widening  
it if it is too low. These pulse width variations provide the  
100K  
1N4148  
Pin 4 or  
Pin 12  
Disable  
290K  
necessary corrections to regulate the magnitude of output  
voltage within its’ specified limits.  
2N3904  
Because the primary portion of the circuit is coupled to the  
150K  
secondary side with magnetic elements, full isolation from  
Pin 2 or  
Pin 8  
input to output is maintained.  
www.irf.com  
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