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AFE8221-Q1 PDF预览

AFE8221-Q1

更新时间: 2022-05-13 23:02:52
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德州仪器 - TI /
页数 文件大小 规格书
59页 1026K
描述
DUAL INTERMEDIATE FREQUENCY (IF) ANALOG FRONT-END FOR DIGITAL RADIO

AFE8221-Q1 数据手册

 浏览型号AFE8221-Q1的Datasheet PDF文件第6页浏览型号AFE8221-Q1的Datasheet PDF文件第7页浏览型号AFE8221-Q1的Datasheet PDF文件第8页浏览型号AFE8221-Q1的Datasheet PDF文件第10页浏览型号AFE8221-Q1的Datasheet PDF文件第11页浏览型号AFE8221-Q1的Datasheet PDF文件第12页 
AFE8221-Q1  
www.ti.com ........................................................................................................................................................................................... SBAS434DECEMBER 2008  
TERMINAL FUNCTIONS (continued)  
TERMINAL  
FUNCTION  
DESCRIPTION  
NAME  
REFCLK  
AVSS  
DVSS  
MCLKI  
MCLKO  
DVDD2  
AVSS  
AVDD  
AVSS  
DVDD  
IOVDD  
DVSS  
IOVSS  
BB_WS  
BB_BCK  
BB_IDAT0  
BB_QDAT0  
BB_IDAT1  
BB_QDAT1  
GRST  
WAKEUP  
IRQ0  
NO.  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
Output  
Ground  
Ground  
Input  
Reference clock output  
Analog ground  
Digital ground (for MCLK oscillator)  
MCLK oscillator input  
MCLK oscillator output  
Output  
Supply  
Ground  
Supply  
Ground  
Supply  
Supply  
Ground  
Ground  
Output  
Output  
Output  
Output  
Output  
Output  
Input  
1.8-V digital supply (for MCLK oscillator)  
Analog ground  
3.3-V analog supply  
Analog ground  
1.8-V digital supply  
3.3-V digital I/O supply  
Digital ground  
Digital I/O ground  
Secondary baseband word select  
Secondary baseband word bit clock  
Secondary baseband channel 0 output (I)  
Secondary baseband channel 0 output (Q)  
Secondary baseband channel 1 output (I)  
Secondary baseband channel 1 output (Q)  
Global reset (active low)  
WAKEUP interrupt output  
Interrupt output 0  
Output  
Output  
Output  
Output  
Input  
IRQ1  
Interrupt output 1  
IRQ2  
Interrupt output 2  
PWD  
Power-down pin (active high)  
Reset pin (active low)  
No connect  
RST  
Input  
NC  
Open  
NC  
Open  
No connect  
NC  
Open  
No connect  
NC  
Open  
No connect  
NC  
Open  
No connect  
NC  
Open  
No connect  
NC  
Open  
No connect  
NC  
Open  
No connect  
NC  
Open  
No connect  
NC  
Open  
No connect  
DVSS  
DVDD  
IOVSS  
IOVDD  
IF_DFSO  
IF_DCLK  
IF_DOUT3  
DVSS  
DVDD  
IF_DOUT2  
Ground  
Supply  
Ground  
Supply  
Output  
Output  
Output  
Ground  
Supply  
Output  
Digital ground  
1.8-V digital supply  
Digital I/O ground  
3.3-V digital I/O supply  
IF interface frame sync  
IF interface bit clock  
IF interface data out 3  
Digital ground  
1.8-V digital supply  
IF interface data out 2  
Copyright © 2008, Texas Instruments Incorporated  
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