Receiver Section
Application Support
The receiver section includes a Receiver Optical SubAs-
sembly (ROSA), pre-amplification and post-amplification
circuit, Clock and Data Recovery Circuit and an electrical
output stage with variable emphasis controls. The ROSA,
containing a high speed PIN detector, pre-amplifier and
imaging optics efficiently couple light from the LC con-
nector interface and perform an optical to electrical con-
version. The resulting differential electrical signal passes
through a post amplification circuit and into a Clock and
Data Recovery circuit (CDR) for cleaning up accumulated
jitter. The resulting signal is passed to a high speed output
An Evaluation Kit and Reference Designs are available to
assist in evaluation of the AFBR-57F5MZ. Please contact
your local Field Sales representative for availability and
ordering details.
Caution
There are no user serviceable parts nor maintenance re-
quirements for the AFBR-57F5MZ. All mechanical adjust-
ments are made at the factory prior to shipment. Tamper-
ing with, modifying, misusing or improperly handling the
AFBR-57F5MZ will void the product warranty. It may also
result in improper operation and possibly overstress the
laser source. Performance degradation or device failure
may result. Connection of the AFBR-57F5MZ to a light
source not compliant with ANSI FC-PI specifications, oper-
ating above maximum operating conditions or in a man-
ner inconsistent with it’s design and function may result in
exposure to hazardous light radiation and may constitute
an act of modifying or manufacturing a laser product. Per-
sons performing such an act are required by law to re-cer-
tify and re-identify the laser product under the provisions
of U.S. 21 CFR (Subchapter J) and TUV.
2
line driver stage with variable, I C-bus controlled, empha-
sis settings allowing the host to optimize signal character-
istics between the SFP and host ASIC. Note the Rx CDR is
engaged only with Rx_RATE=high (16GFC) and bypassed
with Rx_RATE=low (8G/4G).
Receiver Loss of Signal (Rx_LOS)
The post-amplification IC also includes transition detec-
tion circuitry which monitors the ac level of incoming op-
tical signals and provides a TTL/CMOS compatible status
signal to the host (pin 8). An adequate optical input results
in a low Rx_LOS output while a high Rx_LOS output in-
dicates an unusable optical input. The Rx_LOS thresholds
are factory set so that a high output indicates a definite
optical fault has occurred. Rx_LOS can also be monitored
via the two-wire serial interface (address A2h, byte 110,
bit 1).
Ordering Information
Please contact your local field sales engineer or one of
Avago Technologies franchised distributors for ordering
information. For technical information, please visit Avago
Technologies’ WEB page at www.avagotech.com or contact
Avago Technologies Semiconductor Products Customer
Response Center at 1-800-235-0312. For information re-
lated to SFF Committee documentation visit www.sffcom-
mittee.org.
Functional Data I/O
The AFBR-57F5MZ interfaces with the host circuit board
through twenty I/O pins (SFP electrical connector) identi-
fied by function in Table 2. The board layout for this inter-
face is depicted in Figure 6.
Regulatory Compliance
The AFBR-57F5MZ complies with all applicable laws and
regulations as detailed in Table 1. Certification level is de-
pendent on the overall configuration of the host equip-
ment. The transceiver performance is offered as a figure of
merit to assist the designer.
The AFBR-57F5MZ high speed transmit and receive inter-
faces require SFP MSA compliant signal lines on the host
board. To simplify board requirements, biasing resistors
and ac coupling capacitors are incorporated into the SFP
transceiver module (per SFF-8074i) and hence are not re-
quired on the host board. The Tx_Disable, Tx_Fault, and
Rx_LOS lines require TTL lines on the host board (per SFF-
8074i) if used. If an application chooses not to take advan-
tage of the functionality of these pins, care must be taken
to ground Tx_Disable (for normal operation).
Figure 2 depicts the recommended interface circuit to link
the AFBR-57F5MZ to supporting physical layer ICs. Tim-
ing for MSA compliant control signals implemented in the
transceiver are listed in Figure 4.
4
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