OPTICAL INTERFACE
LIGHT FROM FIBER
ELECTRICAL INTERFACE
RD+ (RECEIVE DATA)
RECEIVER
RD- (RECEIVE DATA)
Rx LOSS OF SIGNAL
Rx RATE SELECT RS(0)
Rx Vout &
Emphasis
Rx
CDR
AMPLIFICATION
& QUANTIZATION
PHOTO-DETECTOR
MOD-DEF2 (SDA)
µController
MOD-DEF1 (SCL)
MOD-DEF0
TRANSMITTER
TX_DISABLE
TD+ (TRANSMIT DATA)
LASER
DRIVER &
SAFETY
Tx
CDR
Tx
TD- (TRANSMIT DATA)
TX_FAULT
LIGHT TO FIBER
VCSEL
Equalization
CIRCUITRY
Tx RATE SELECT RS(1)
Figure 1. Transceiver functional diagram.
Transmitter Section
The transmitter section includes a Transmitter Optical
SubAssembly (TOSA), laser driver circuit, Clock and Data
Recovery circuit (CDR) and an electrical input stage with
variable equalization controls and electrical eye mea-
surement capability. The TOSA contains a 850 nm Vertical
Cavity Surface Emitting Laser (VCSEL) light source with
integral light monitoring function and imaging optics to
assure efficient optical coupling to the LC connector in-
terface. The TOSA is driven by a laser driver IC, which uses
the differential output from an integral Tx CDR stage to
modulate and regulate VCSEL optical power. As mandated
by FC-PI-5, the integral CDR cleans up any incoming jit-
ter accumulated from the host ASIC, PCB traces and SFP
electrical connector. Between the SFP electrical connector
tween successive assertions of this control signal. Tx_Dis-
able can also be asserted via the two-wire serial interface
(address A2h, byte 110, bit 6) and monitored (address
A2h, byte 110, bit 7).
The contents of A2h, byte 110, bit 6 are logic OR’d with
hardware Tx_Disable (pin 3) to control transmitter opera-
tion.
Transmit Fault (Tx_Fault)
A catastrophic laser fault will activate the transmitter sig-
nal, TX_FAULT, and disable the laser. This signal is an open
collector output (pull-up required on the host board). A
low signal indicates normal laser operation and a high
signal indicates a fault. The TX_FAULT will be latched high
when a laser fault occurs and is cleared by toggling the
TX_DISABLE input or power cycling the transceiver. The
transmitter fault condition can also be monitored via the
two-wire serial interface (address A2, byte 110, bit 2).
2
and Tx CDR is a variable, I C-bus controlled, equalization
circuit to optimize SFP performance with non-ideal in-
coming electrical waveforms. Note the Tx CDR is engaged
only with Tx_RATE=high (16GFC) and bypassed with Tx_
RATE=low (8G/4G).
Eye Safety Circuit
Transmit Disable (Tx_Disable)
The AFBR-57F5MZ provides Class 1 (single fault tolerant)
eye safety by design and has been tested for compliance
with the requirements listed in Table 1. The eye safety
circuit continuously monitors the optical output power
level and will disable the transmitter upon detecting an
unsafe condition beyond the scope of Class 1 certification.
Such unsafe conditions can be due to inputs from the host
board (Vcc fluctuation, unbalanced code) or a fault within
the transceiver.
The AFBR-57F5MZ accepts a TTL and CMOS compatible
transmit disable control signal input (pin 3) which shuts
down the transmitter optical output. A high signal im-
plements this function while a low signal allows normal
transceiver operation. In the event of a fault (e.g. eye safe-
ty circuit activated), cycling this control signal resets the
module as depicted in Figure 4. An internal pull up resistor
disables the transceiver transmitter until the host pulls the
input low. Host systems should allow a 10 ms interval be-
3
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