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AFBR-5715PZ PDF预览

AFBR-5715PZ

更新时间： 2024-02-26 19:37:22
品牌 Logo 应用领域
安华高科 - AVAGO 光纤放大器通信
页数 文件大小 规格书
20页 508K
描述
Families of Multi-Mode Small Form Factor Pluggable (SFP) Optical Transceivers

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AFBR-5715PZ 技术参数

是否Rohs认证： 符合生命周期：Transferred
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8517.62.00.50风险等级：5.71
Is Samacsys：N主体宽度：16.25 mm
主体高度：12.1 mm主体长度或直径：42.3 mm
内置特性：AMPLIFIER通信标准：GR-468
连接类型：LC CONNECTOR数据速率（发送）：1250 Mbps
发射极/检测器类型：LASER DIODE光纤设备类型：TRANSCEIVER
光纤类型：50/125, MMFJESD-609代码：e4
安装特点：PANEL MOUNT最高工作温度：85 °C
最低工作温度：-10 °C最大工作波长：860 nm
最小工作波长：830 nm标称工作波长：850 nm
标称光功率输出：0.223 mW灵敏度：-21 dBm
子类别：Fiber Optic Transceivers最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：NO端子面层：Gold (Au)
Base Number Matches：1

AFBR-5715PZ 数据手册

 浏览型号AFBR-5715PZ的Datasheet PDF文件第1页浏览型号AFBR-5715PZ的Datasheet PDF文件第2页浏览型号AFBR-5715PZ的Datasheet PDF文件第3页浏览型号AFBR-5715PZ的Datasheet PDF文件第5页浏览型号AFBR-5715PZ的Datasheet PDF文件第6页浏览型号AFBR-5715PZ的Datasheet PDF文件第7页 
Functional I/O  
Digital Diagnostic Interface and Serial Identification  
(EEPROM)  
The AFBR-571xZ accepts industry standard differential  
signals such as LVPECL and CML within the scope of the  
SFP MSA. To simplify board requirements, transmitter bias  
resistors and ac coupling capacitors are incorporated, per  
SFF-8074i, and hence are not required on the host board.  
The module is AC-coupled and internally terminated.  
The entire AFBR-571xZ family complies with the SFF-  
8074i SFP specification. The AFBR-5715Z family further  
complies with SFF-8472, the SFP specification for Digital  
Diagnostic Monitoring Interface. Both specifications can  
be found at http://www.sffcommittee.org.  
Figure 3 illustrates a recommended interface circuit to  
link the AFBR-571xZ to the supporting Physical Layer  
integrated circuits.  
The AFBR-571xZ features an EEPROM for Serial ID, which  
contains the product data stored for retrieval by host  
equipment. This data is accessed via the 2-wire serial  
EEPROM protocol of the ATMEL AT24C01A or similar, in  
compliance with the industry standard SFP Multi-Source  
Agreement. The base EEPROM memory, bytes 0-255 at  
memory address 0xA0, is organized in compliance with  
SFF-8074i. Contents of this serial ID memory are shown  
in Table 10.  
Timing diagrams for the MSA compliant control signals  
implemented in this module are depicted in Figure 6.  
The AFBR-571xZ interfaces with the host circuit board  
through twenty I/O pins (SFP electrical connector)  
identified by function in Table 2. The AFBR-571xZ high  
speed transmit and receive interfaces require SFP MSA  
compliant signal lines on the host board. The Tx_Disable,  
Tx_Fault, and Rx_LOS lines require TTL lines on the host  
board (per SFF-8074i) if used. If an application chooses  
not to take advantage of the functionality of these pins,  
care must be taken to ground Tx_Disable (for normal  
operation).  
The I2C accessible memory page address 0xB0 is used  
internally by SFP for the test and diagnostic purposes  
and it is reserved.  
1 µH  
V
T,R  
CC  
HOUSING  
GROUND  
10 µF  
0.1 µF  
1 µH  
AVAGO  
AFBR-571xZ  
V
T
CC  
*RES  
0.1  
µF  
*RES  
TX_DISABLE  
TX_FAULT  
50 Ω  
50 Ω  
TD+  
C
R
C
SO1+  
LASER DRIVER  
& EYE SAFETY  
CIRCUITRY  
TX[0:9]  
SO1–  
TD–  
SYNC  
LOOP  
VEET  
AVAGO  
HDMP-1687  
RX[0:9]  
V
R
CC  
10  
µF  
0.1  
µF  
MAC  
ASIC  
RD+  
RD–  
50 Ω  
50 Ω  
SYN1  
RC1(0:1)  
RCM0  
SI1+  
SI1–  
C
C
R
AMPLIFICATION  
&
QUANTIZATION  
RFCT  
REF_RATE  
V
T,R  
CC  
*RES  
*RES  
*RES  
*RES  
RX_LOS  
MOD_DEF2  
MOD_DEF1  
MOD_DEF0  
EEPROM  
REFCLK  
VEER  
125 MHz  
NOTE: * 4.7 k Ω < RES < 10 kΩ  
Figure 3. Typical application configuration.  
4
1234567...20

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