ADuM5401/ADuM5402/ADuM5403/ADuM5404
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V ≤ VDD1 ≤ 5.5 V, VSEL = VISO; all voltages are relative to their respective ground. All minimum/maximum specifications apply over the
entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5.0 V, VSEL = VISO = 5.0 V.
Table 1.
Parameter
Symbol
Min
Typ
Max
5.4
5
Unit
Test Conditions/Comments
DC-TO-DC CONVERTER POWER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
VISO
4.7
5.0
1
1
V
IISO = 0 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 10 mA to 90 mA
VISO(LINE)
VISO(LOAD)
VISO(RIP)
mV/V
%
mV p-p
75
20 MHz bandwidth, CBO = 0.1 μF║10 μF,
IISO = 90 mA
Output Noise
VISO(N)
200
mV p-p
20 MHz bandwidth, CBO = 0.1 μF║10 μF,
IISO = 90 mA
Switching Frequency
fOSC
fPWM
180
625
MHz
kHz
Pulse-Width Modulation Frequency
iCoupler DATA CHANNELS
DC to 2 Mbps Data Rate1
Maximum Output Supply Current2
Efficiency at Maximum Output Supply
Current3
IDD1 Supply Current, No VISO Load
25 Mbps Data Rate (CRWZ Grade Only)
IDD1 Supply Current, No VISO Load
ADuM5401
IISO(MAX)
100
mA
%
f ≤ 1 MHz, VISO > 4.5 V
IISO = IISO(2,MAX), f ≤ 1 MHz
34
19
IDD1(Q)
IDD1(D)
30
mA
IISO = 0 mA, f ≤ 1 MHz
68
71
75
78
mA
mA
mA
mA
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
ADuM5402
ADuM5403
ADuM5404
Available VISO Supply Current4
IISO(LOAD)
ADuM5401
ADuM5402
ADuM5403
ADuM5404
87
85
83
81
mA
mA
mA
mA
mA
μA
V
CL = 15 pF, f = 12.5 MHz
CL = 15 pF, f = 12.5 MHz
CL = 15 pF, f = 12.5 MHz
CL = 15 pF, f = 12.5 MHz
IDD1 Supply Current, Full VISO Load
I/O Input Currents
Logic High Input Threshold
IDD1(MAX)
IIA, IIB, IIC, IID
VIH
290
+0.01 +20
CL = 0 pF, f = 0 MHz, VDD = 5 V, IISO = 100 mA
−20
0.7 × VISO,
0.7 × VIDD1
Logic Low Input Threshold
Logic High Output Voltages
VIL
0.3 × VISO,
0.3 ×
VIDD1
V
VOAH, VOBH
VOCH, VODH
,
VDD1 − 0.3, 5.0
VISO − 0.3
VDD1 − 0.5, 4.8
VISO − 0.3
V
V
V
V
I
I
I
Ox = −20 μA, VIx = VIxH
Ox = −4 mA, VIx = VIxH
Ox = 20 μA, VIx = VIxL
Logic Low Output Voltages
AC SPECIFICATIONS
VOAL, VOBL
VOCL, VODL
,
0.0
0.1
0.4
0.0
IOx = 4 mA, VIx = VIxL
ADuM5401ARWZ/ADuM5402ARWZ/
ADuM5403ARWZ/ADuM5404ARWZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew
PW
1000
ns
Mbps
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
tPHL, tPLH
PWD
tPSK
55
100
40
50
|
Channel-to-Channel Matching
tPSKCD/tPSKOD
50
ns
Rev. 0 | Page 3 of 24