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ADUM5201ARWZ

更新时间： 2024-02-15 17:00:14
品牌 Logo 应用领域
亚德诺 - ADI 转换器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
24页 544K
描述
Dual Channel Isolators with Integrated DC-to-DC Converter

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ADUM5201ARWZ 技术参数

Source Url Status Check Date：2013-05-01 14:56:51.099是否无铅： 含铅
是否Rohs认证： 符合生命周期：Active
包装说明：SOP,针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8543.70.99.60风险等级：5.6
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
湿度敏感等级：3功能数量：1
端子数量：16最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
筛选级别：AEC-Q100座面最大高度：2.65 mm
最大供电电压：5.5 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

ADUM5201ARWZ 数据手册

 浏览型号ADUM5201ARWZ的Datasheet PDF文件第3页浏览型号ADUM5201ARWZ的Datasheet PDF文件第4页浏览型号ADUM5201ARWZ的Datasheet PDF文件第5页浏览型号ADUM5201ARWZ的Datasheet PDF文件第7页浏览型号ADUM5201ARWZ的Datasheet PDF文件第8页浏览型号ADUM5201ARWZ的Datasheet PDF文件第9页 
ADuM5200/ADuM5201/ADuM5202  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
AC SPECIFICATIONS  
ADuM520xARWZ  
Minimum Pulse Width7  
Maximum Data Rate  
Propagation Delay  
Pulse Width Distortion, |tPLH − tPHL  
Propagation Delay Skew  
Channel-to-Channel Matching  
ADuM520xCRWZ  
PW  
1000  
ns  
Mbps  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
1
tPHL, tPLH  
PWD  
tPSK  
60  
100  
40  
50  
|
tPSKCD, tPSKOD  
50  
ns  
Minimum Pulse Width7  
Maximum Data Rate  
Propagation Delay  
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew  
PW  
40  
ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
25  
tPHL, tPLH  
PWD  
45  
5
60  
6
|
ns  
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
45  
6
Channel-to-Channel Matching,  
Codirectional Channels  
Channel-to-Channel Matching,  
tPSKOD  
15  
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels  
For All Models  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity  
at Logic High Output  
Common-Mode Transient Immunity  
at Logic Low Output  
Refresh Rate  
tR/tF  
|CMH|  
2.5  
35  
ns  
kV/ꢀs  
CL = 15 pF, CMOS signal levels  
VIx = VDD or VISO, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, V = 1000 V,  
transient magnitude = 800 V  
25  
25  
|CML|  
fr  
35  
kV/ꢀs  
Mbps  
1.0  
1 The contributions of supply current values for all four channels are combined at identical data rates.  
2 VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps data I/O channels draw additional current  
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the  
Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the VISO power budget.  
3 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power  
consumed by the I/O channels as part of its internal power consumption.  
4 IDD1(D) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load representing the  
maximum dynamic load conditions. Treat resistive loads on the outputs separately from the dynamic load.  
5 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load  
representing the maximum dynamic load conditions. Refer to the Power Consumption section for the calculation of available current at less than the maximum data rate.  
6 Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built  
into the detection threshold to prevent oscillations and noise sensitivity.  
7 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.  
Rev. 0 | Page 6 of 24  
 
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ADUM5201ARWZ-RL ADI Dual-Channel, 2.5 kV Isolators with Integrated DC-to-DC Converter

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ADUM5201CRWZ ADI Dual Channel Isolators with Integrated DC-to-DC Converter

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ADUM5201CRWZ1 ADI Dual-Channel Isolators with Integrated DC/DC Converter

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