Data Sheet
ADuM4120/ADuM4120-1
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Low-side voltages referenced to GND
1
. High-side voltages referenced to GND2; 2.5 V ≤ VDD1 ≤ 6.5 V; 4.5 V ≤ VDD2 ≤ 35 V, and T = −40°C
J
to +125°C. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All
typical specifications are at TJ = 25°C, VDD1 = 5.0 V, and VDD2 = 15 V, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
4.5
2.5
−1
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
High-Side Power Supply
VDD2 Input Voltage
VDD2 Input Current, Quiescent
Logic Supply
VDD1 Input Voltage
Input Current
Logic Input
VDD2
IDD2(Q)
35
2.6
V
mA
1.7
VDD1
IDD1
VIN
6.5
5
V
mA
3.6
VIN = high
VIN Input Current
Logic Input Voltage
High
IVIN
0.01
+1
μA
VIH
VIL
0.7 × VDD1
3.5
V
V
V
V
2.5 V ≤ VDD1 ≤ 5 V
VDD1 > 5 V
2.5 V ≤ VDD1 ≤ 5 V
VDD1 > 5 V
Low
0.3 × VDD1
1.5
Undervoltage Lockout (UVLO)
VDD1
Positive Going Threshold
Negative Going Threshold
Hysteresis
VVDD1UV+
VVDD1UV−
VVDD1UVH
2.45
2.35
0.1
2.5
V
V
V
2.3
VDD2
Grade A
Positive Going Threshold
Negative Going Threshold
Hysteresis
VVDD2UV+
VVDD2UV−
VVDD2UVH
4.4
4.2
0.2
4.5
V
V
V
4.1
Grade B
Positive Going Threshold
Negative Going Threshold
Hysteresis
VVDD2UV+
VVDD2UV−
VVDD2UVH
7.3
7.1
0.2
7.5
V
V
V
6.9
Grade C
Positive Going Threshold
Negative Going Threshold
Hysteresis
VVDD2UV+
VVDD2UV−
VVDD2UVH
11.3
11.1
0.2
11.6
V
V
V
10.8
Thermal Shutdown (TSD)
TSD Positive Edge
TSD Hysteresis
TTSD_POS
TTSD_HYST
RDSON_N
155
30
°C
°C
Ω
Ω
Ω
Ω
A
Internal NMOS Gate Resistance
0.6
0.6
0.8
0.8
2.3
1.6
1.6
1.8
1.8
Tested at 250 mA, VDD2 = 15 V
Tested at 1 A, VDD2 = 15 V
Tested at 250 mA, VDD2 = 15 V
Tested at 1 A, VDD2 = 15 V
Internal PMOS Gate Resistance
Peak Output Current
RDSON_P
IPK
VDD2 = 12 V, 4 Ω gate resistance
Rev. 0 | Page 3 of 17