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ADUM3400_15 PDF预览

ADUM3400_15

更新时间: 2022-02-26 11:59:13
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 436K
描述
Quad-Channel, Digital Isolators, Enhanced System-Level ESD Reliability

ADUM3400_15 数据手册

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Data Sheet  
ADuM3400/ADuM3401/ADuM3402  
Parameter  
Symbol  
PWD  
tPSK  
Min  
Typ Max Unit  
Test Conditions  
4
Pulse Width Distortion, |tPLH − tPHL  
|
40  
50  
50  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Propagation Delay Skew5  
Channel-to-Channel Matching6  
ADuM340xBRW  
tPSKCD/OD  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
100 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
20  
Propagation Delay4  
tPHL, tPLH  
PWD  
38  
5
50  
3
4
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
ns  
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
22  
3
Channel-to-Channel Matching,  
tPSKOD  
6
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels6  
ADuM340xCRW  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
8.3  
120  
34  
0.5  
3
11.1 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
90  
20  
Propagation Delay4  
tPHL, tPLH  
PWD  
45  
2
4
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
ns  
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
16  
2
Channel-to-Channel Matching,  
tPSKOD  
5
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels6  
For All Models  
Output Disable Propagation Delay  
(High/Low-to-High Impedance)  
Output Enable Propagation Delay  
(High Impedance-to-High/Low)  
tPHZ, tPLH  
tPZH, tPZL  
6
6
8
8
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Output Rise/Fall Time (10% to 90%)  
tR/tF  
3
ns  
Common-Mode Transient Immunity  
at Logic High Output7  
Common-Mode Transient Immunity  
at Logic Low Output7  
|CMH|  
25  
25  
35  
kV/µs  
VIx = VDD1/VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
|CML|  
35  
kV/µs  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.1  
Mbps  
Input Dynamic Supply Current per Channel8 IDDI (D)  
Output Dynamic Supply Current per Channel8 IDDO (D)  
0.10  
0.03  
mA/Mbps  
mA/Mbps  
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load  
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.  
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through  
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.  
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.  
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.  
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load  
within the recommended operating conditions.  
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of  
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with  
inputs on opposing sides of the isolation barrier.  
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate  
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient  
magnitude is the range over which the common mode is slewed.  
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information  
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current  
for a given data rate.  
Rev. C | Page 7 of 24  
 
 

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