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ADUM3400_15

更新时间： 2022-02-26 11:59:13
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 436K
描述
Quad-Channel, Digital Isolators, Enhanced System-Level ESD Reliability

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ADUM3400_15 数据手册

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ADuM3400/ADuM3401/ADuM3402  
Data Sheet  
Parameter  
Symbol  
Min  
Typ Max Unit  
Test Conditions  
SWITCHING SPECIFICATIONS  
ADuM340xARW  
Minimum Pulse Width2  
Maximum Data Rate3  
Propagation Delay4  
Pulse Width Distortion, |tPLH − tPHL  
Propagation Delay Skew5  
Channel-to-Channel Matching6  
ADuM340xBRW  
PW  
1000 ns  
Mbps  
100 ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
1
50  
tPHL, tPLH  
PWD  
tPSK  
65  
4
|
40  
50  
50  
ns  
ns  
ns  
tPSKCD/OD  
Minimum Pulse Width2  
Maximum Data Rate3  
Propagation Delay4  
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew5  
PW  
100 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
20  
tPHL, tPLH  
PWD  
32  
5
50  
3
4
|
ns  
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
15  
3
Channel-to-Channel Matching,  
Codirectional Channels6  
Channel-to-Channel Matching,  
tPSKOD  
6
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels6  
ADuM340xCRW  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
8.3  
120  
27  
0.5  
3
11.1 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
90  
18  
Propagation Delay4  
tPHL, tPLH  
PWD  
32  
2
4
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
ns  
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
10  
2
Channel-to-Channel Matching,  
tPSKOD  
5
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels6  
For All Models  
Output Disable Propagation Delay  
(High/Low-to-High Impedance)  
Output Enable Propagation Delay  
(High Impedance-to-High/Low)  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity  
at Logic High Output7  
t
PHZ, tPLH  
6
6
8
8
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
VIx = VDD1/VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
tPZH, tPZL  
tR/tF  
|CMH|  
2.5  
35  
ns  
kV/µs  
25  
25  
Common-Mode Transient Immunity  
at Logic Low Output7  
|CML|  
35  
kV/µs  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.2  
0.20  
0.05  
Mbps  
mA/Mbps  
mA/Mbps  
Input Dynamic Supply Current per Channel8  
IDDI (D)  
Output Dynamic Supply Current per Channel8 IDDO (D)  
Rev. C | Page 4 of 24  
1234567...24

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