ADuM3220/ADuM3221
Data Sheet
APPLICATIONS INFORMATION
PC BOARD LAYOUT
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
The ADuM3220/ADuM3221 digital isolators require no exter-
nal interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins, as
shown in Figure 19. Use a small ceramic capacitor with a value
from 0.01 µF to 0.1 µF to provide a good high frequency bypass.
On the output power supply pin, VDD2, it is recommended that a
10 µF capacitor also be added to provide the charge required to
drive the gate capacitance at the ADuM3220/ADuM3221 outputs.
On the output supply pin, the use of vias with the bypass capacitor
should be avoided, or multiple vias should be used to reduce the
inductance in the bypassing. The total lead length between both
ends of the smaller capacitor and the input or output power
supply pin should not exceed 20 mm.
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal pad
beneath the part; therefore, heat is dissipated mainly through
the package pins.
Package thermal dissipation limits the performance of switching
frequency vs. output load, as illustrated in Figure 8, which shows
the maximum load capacitance that can be driven with a 1 Ω series
gate resistor for different values of output voltage. For example,
this curve shows that a typical ADuM3220/ADuM3221 can drive
a large MOSFET with 120 nC gate charge at 8 V output (which is
equivalent to a 15 nF load) up to a frequency of about 300 kHz.
OUTPUT LOAD CHARACTERISTICS
V
V
DD1
DD2
V
V
V
V
IA
IB
OA
OB
The ADuM3220/ADuM3221 output signals depend on the
characteristics of the output load, which is typically an N-channel
MOSFET. The driver output response to an N-channel MOSFET
load can be modeled with a switch output resistance (RSW), an
inductance due to the printed circuit board trace (LTRACE), a series
gate resistor (RGATE), and a gate-to-source capacitance (CGS), as
shown in Figure 21.
GND
GND
1
2
Figure 19. Recommended PCB Layout
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a
logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output. The ADuM3220/ADuM3221 specify tDLH
as the time between the input rising high logic threshold, VIH,
and the output rising 10% threshold (see Figure 20). Likewise, the
falling propagation delay, tDHL, is defined as the time between the
input falling logic low threshold, VIL, and the output falling 90%
threshold. The rise and fall times are dependent on the loading
conditions and are not included in the propagation delay, as is
the industry standard for gate drivers.
R
R
SW
GATE
V
V
OA
IA
V
ADuM3220/
ADuM3221
O
L
TRACE
C
GS
Figure 21. RLC Model of the Gate of an N-Channel MOSFET
RSW is the switch resistance of the internal ADuM3220/ADuM3221
driver output, which is about 1.5 Ω. RGATE is the intrinsic gate
resistance of the MOSFET and any external series resistance. A
MOSFET that requires a 4 A gate driver has a typical intrinsic
gate resistance of about 1 Ω and a gate-to-source capacitance,
CGS, from 2 nF to 10 nF. LTRACE is the inductance of the printed
circuit board trace, typically a value of 5 nH or less for a well-
designed layout with a very short and wide connection from the
ADuM3220/ADuM3221 output to the gate of the MOSFET.
90%
OUTPUT
10%
V
The following equation defines the Q factor of the RLC circuit,
which indicates how the ADuM3220/ADuM3221 output responds
to a step change. For a well-damped output, Q is less than 1.
Adding a series gate resistor dampens the output response.
IH
INPUT
V
IL
tDHL
tDLH
tR
tF
LTRACE
CGS
1
Q =
×
(RSW + RGATE
)
Figure 20. Propagation Delay Parameters
In Figure 5 and Figure 6, the ADuM3220/ADuM3221 output
waveforms for 10 V output are shown for a CGS of 2 nF and 1 nF,
respectively. Note the ringing of the output in Figure 6 with CGS
of 1 nF and a calculated Q factor of 1.5, where less than 1 is
desired for good damping.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM3220/ADuM3221 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM3220/
ADuM3221 components operating under the same conditions.
Rev. C | Page 12 of 16
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