Data Sheet
ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
6.6
150
4.8
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
tPHL, tPLH
PWD
7.2
0.5
1.5
13
3
|tPLH − tPHL|
tPSK
6.1
Between any two units at the
same temperature, voltage, and load
Channel Matching
Codirectional
Opposing Direction
Jitter
tPSKCD
tPSKOD
0.5
0.5
490
70
3.0
3.0
ns
ns
ps p-p
ps rms
See the Jitter Measurement section
See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
VIH
VIL
0.7 × VDDx
V
V
Logic Low
0.3 × VDDx
Output Voltage
Logic High
3
VOH
VOL
VDDx − 0.1 VDDx
VDDx − 0.4 VDDx − 0.2
V
V
V
V
IOx2 = −20 μA, VIx = VIxH
3
IOx2 = −4 mA, VIx = VIxH
4
Logic Low
0.0
0.2
0.1
0.4
IOx2 = 20 μA, VIx = VIxL
4
IOx2 = 4 mA, VIx = VIxL
Input Current per Channel
II
−10
−10
+0.01
−3
9
+10
μA
μA
μA
μA
0 V ≤ VIx ≤ VDDx
VE2 = 0 V
DISABLE1 = VDDx
0 V ≤ VOx ≤ VDDx
VE2 Enable Input Pull-Up Current
DISABLE1 Input Pull-Down Current
Tristate Output Current per Channel
Quiescent Supply Current
IPU
IPD
IOZ
15
+10
−10
+0.01
ADuM240D/ADuM240E
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.2
2.0
12.0
2.0
2.2
mA
mA
mA
mA
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
2.72
20.0
2.92
ADuM241D/ADuM241E
ADuM242D/ADuM242E
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.9
10.0
6.0
2.46
2.62
17.0
10.0
mA
mA
mA
mA
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0(E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
1.6
1.6
7.0
7.0
2.46
2.46
11.5
11.5
mA
mA
mA
mA
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 0 (E0, D0), 1 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
VI5 = 1 (E0, D0), 0 (E1, D1)6
Dynamic Supply Current
Dynamic Input
Dynamic Output
IDDI (D)
IDDO (D)
0.01
0.02
mA/Mbps Inputs switching, 50% duty cycle
mA/Mbps Inputs switching, 50% duty cycle
Rev. D | Page 3 of 26