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ADUM2402

更新时间： 2024-02-23 10:16:57
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
23页 206K
描述
Quad-Channel Digital Isolators, 5KV

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ADUM2402 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOIC-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8543.70.99.60风险等级：1.32
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/421405.3.2.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=421405
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=4214053D View：https://componentsearchengine.com/viewer/3D.php?partID=421405
Samacsys PartID：421405Samacsys Image：https://componentsearchengine.com/Images/9/ADUM2402CRWZ.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/3/ADUM2402CRWZ.jpgSamacsys Pin Count：16
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：RW-16 (SOIC)Samacsys Released Date：2017-01-11 11:21:59
Is Samacsys：N接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：10.3 mm湿度敏感等级：1
功能数量：1端子数量：16
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：2.65 mm最大供电电压：5.5 V
最小供电电压：2.7 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

ADUM2402 数据手册

 浏览型号ADUM2402的Datasheet PDF文件第16页浏览型号ADUM2402的Datasheet PDF文件第17页浏览型号ADUM2402的Datasheet PDF文件第18页浏览型号ADUM2402的Datasheet PDF文件第20页浏览型号ADUM2402的Datasheet PDF文件第21页浏览型号ADUM2402的Datasheet PDF文件第22页 
Preliminary Technical Data  
ADuM2400/ADuM2401/ADuM2402  
APPLICATION INFORMATION  
Propagation delay skew refers to the maximum amount the  
propagation delay differs among multiple ADuM240x  
components operated under the same conditions.  
PC BOARD LAYOUT  
The ADuM240x digital isolator requires no external interface  
circuitry for the logic interfaces. Power supply bypassing is  
strongly recommended at the input and output supply pins  
(Figure 17). Bypass capacitors are most conveniently connected  
between Pins 1 and 2 for VDD1 and between Pins 15 and 16 for  
VDD2. The capacitor value should be between 0.01 µF and 0.1 µF.  
The total lead length between both ends of the capacitor and  
the input power supply pin should not exceed 20 mm.  
Bypassing between Pins 1 and 8 and between Pins 9 and 16  
should also be considered unless the ground pair on each  
package side are connected close to the package.  
DC CORRECTNESS AND MAGNETIC FIELD  
IMMUNITY  
Positive and negative logic transitions at the isolator input cause  
narrow (~1 ns) pulses to be sent via the transformer to the  
decoder. The decoder is bistable and is therefore either set or  
reset by the pulses indicating input logic transitions. In the  
absence of logic transitions at the input for more than 2 µs, a  
periodic set of "refresh" pulses indicative of the correct input  
state are sent to ensure "dc correctness" at the output. If the  
decoder receives no pulses for more than about 5 µs, the input  
side is assumed to be unpowered or nonfunctional, in which  
case the isolator output is forced to a default state (see Table 10)  
by the watchdog timer circuit.  
V
V
DD2  
DD1  
GND  
V
V
GND  
1
2
V
IA  
IB  
OA  
V
OB  
V
V
V
V
V
IC/OC  
ID/OD  
OC/IC  
OD/ID  
E2  
V
E1  
GND  
GND  
1
2
The limitation on the ADuM240x’s magnetic field immunity is  
set by the condition in which induced voltage in the transformer’s  
“receiving” coil is sufficiently large to either falsely set or reset the  
decoder. The analysis below defines the conditions under which  
this may occur. The 3 V operating condition of the ADuM240x is  
examined as it represents the most susceptible mode of operation.  
Figure 17. Recommended Printed Circuit Board Layout  
In applications involving high common-mode transients, care  
should be taken to ensure that board coupling across the  
isolation barrier is minimized. Furthermore, the board layout  
should be designed such that any coupling that does occur  
equally affects all pins on a given component side. Failure to  
ensure this could cause voltage differentials between pins  
exceeding the device’s Absolute Maximum Ratings, thereby  
leading to latch-up or permanent damage.  
The pulses at the transformer output have an amplitude greater than  
1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore  
establishing a 0.5 V margin in which induced voltages can be  
tolerated. The voltage induced across the “receiving” coil is given by:  
2
V = (–dβ/dt)∑∏rn ; n = 1, 2,…, N  
PROPAGATION DELAY-RELATED PARAMETERS  
Propagation delay is a parameter that describes the length of  
time it takes for a logic signal to propagate through a  
component. The propagation delay to a logic low output may  
differ from the propagation delay to a logic high.  
where:  
β is magnetic flux density (gauss)  
N is the number of turns in the receiving coil.  
rn is the radius of the nth turn in the receiving coil (cm).  
Given the geometry of the receiving coil in the ADuM240x and  
an imposed requirement that the induced voltage be at most  
50% of the 0.5 V margin at the decoder, a maximum allowable  
magnetic field is calculated as shown in below in Figure 19.  
INPUT (V  
)
50%  
IX  
tPLH  
tPHL  
OUTPUT (V  
)
50%  
OX  
Figure 18. Propagation Delay Parameters  
Pulsewidth distortion is the maximum difference between these  
two propagation delay values and is an indication of how  
accurately the input signal’s timing is preserved.  
Channel-to-channel matching refers to the maximum amount  
the propagation delay differs among channels within a single  
ADuM240x component.  
Rev. PrD | Page 19 of 23  
1...1617181920212223

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