Preliminary Technical Data
ADuM2400/ADuM2401/ADuM2402
Parameter
Symbol Min
Typ Max Unit
Test Conditions
5 V/3 V Operation
3 V/5 V Operation
62
34
82
52
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM2402, Total Supply Current, Four Channels2
IDD2(90)
19
35
27
43
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
IDD1(Q)
1.5
0.9
2.1
1.5
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
IDD2(Q)
0.9
1.5
1.5
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
3 V/5 V Operation
10 Mbps (BRWZ and CRWZ Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1(10)
5.6
3.0
7.0
4.2
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
IDD2(10)
3.0
5.6
4.2
7.0
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
90 Mbps (CRWZ Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1(90)
49
27
62
39
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
IDD2(90)
27
49
39
62
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
For All Models
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
–10
0.01 10
µA
0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2,
0 ≤ VE1,VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
5 V/3 V Operation
VIH, VEH
2.0
1.6
V
V
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
VIL, VEL
0.8
0.4
V
V
V
VOAH, VOBH
VOCH, VODH
,
VDD1/VDD2 – 0.1 VDD1/
VDD2
IOx = –20 µA, VIx = VIxH
IOx = –4 mA, VIx = VIxH
V
DD1/VDD2 – 0.4 VDD1
/
V
VDD2
– 0.2
Logic Low Output Voltages
VOAL,VOBL,
VOCL, VODL
0.0
0.04 0.1
0.2
0.1
V
V
V
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0.4
SWITCHING SPECIFICATIONS
ADuM240xARW
Minimum Pulsewidth3
Maximum Data Rate4
PW
1000 ns
Mbps
ns
CL = 15pF, CMOS signal levels
CL = 15pF, CMOS signal levels
CL = 15pF, CMOS signal levels
CL = 15pF, CMOS signal levels
CL = 15pF, CMOS signal levels
CL = 15pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
70
100
40
5
Pulsewidth Distortion, |tPLH – tPHL
|
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM240xBRW
50
50
tPSKCD/OD
Rev. PrD | Page 9 of 23