5秒后页面跳转
捷配首页

Datasheet > 信号电路 > 其他模拟IC> ADUM1401ARWZ-RL
ADUM1401ARWZ-RL PDF预览

ADUM1401ARWZ-RL

更新时间： 2024-02-27 14:28:03
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 794K
描述
Quad-Channel Digital Isolators

阅读下载

获取价格

ADUM1401ARWZ-RL 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8543.70.99.60风险等级：1.1
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/297079.1.2.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=297079
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=2970793D View：https://componentsearchengine.com/viewer/3D.php?partID=297079
Samacsys PartID：297079Samacsys Image：https://componentsearchengine.com/Images/9/ADUM1401WTRWZ.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/ADUM1401WTRWZ.jpgSamacsys Pin Count：16
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：RW-16 (SOIC)Samacsys Released Date：2020-04-08 14:02:48
Is Samacsys：N其他特性：ALSO OPERATES AT 5V NOMINAL
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
湿度敏感等级：1功能数量：4
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Other Analog ICs最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmBase Number Matches：1

ADUM1401ARWZ-RL 数据手册

 浏览型号ADUM1401ARWZ-RL的Datasheet PDF文件第2页浏览型号ADUM1401ARWZ-RL的Datasheet PDF文件第3页浏览型号ADUM1401ARWZ-RL的Datasheet PDF文件第4页浏览型号ADUM1401ARWZ-RL的Datasheet PDF文件第6页浏览型号ADUM1401ARWZ-RL的Datasheet PDF文件第7页浏览型号ADUM1401ARWZ-RL的Datasheet PDF文件第8页 
ADuM1400/ADuM1401/ADuM1402  
Parameter  
Pulse Width Distortion, |tPLH − tPHL  
Symbol  
Min  
Typ Max Unit  
Test Conditions  
5
PWD  
40  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
|
Change vs. Temperature  
Propagation Delay Skew6  
Channel-to-Channel Matching7  
ADuM140xBRW  
11  
ps/°C  
ns  
ns  
tPSK  
tPSKCD/tPSKOD  
50  
50  
Minimum Pulse Width3  
Maximum Data Rate4  
Propagation Delay5  
PW  
100 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
20  
tPHL, tPLH  
PWD  
32  
5
50  
3
5
ns  
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew6  
|
ps/°C  
ns  
tPSK  
15  
3
Channel-to-Channel Matching, Codirectional  
Channels7  
tPSKCD  
ns  
Channel-to-Channel Matching, Opposing-  
Directional Channels7  
tPSKOD  
6
ns  
CL = 15 pF, CMOS signal levels  
ADuM140xCRW  
Minimum Pulse Width3  
Maximum Data Rate4  
Propagation Delay5  
PW  
8.3  
120  
27  
0.5  
3
11.1 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
90  
18  
tPHL, tPLH  
PWD  
32  
2
5
ns  
Pulse Width Distortion, |tPLH − tPHL  
|
Change vs. Temperature  
Propagation Delay Skew6  
ps/°C  
ns  
tPSK  
10  
2
Channel-to-Channel Matching, Codirectional  
Channels7  
tPSKCD  
ns  
Channel-to-Channel Matching, Opposing-  
Directional Channels7  
tPSKOD  
5
ns  
CL = 15 pF, CMOS signal levels  
For All Models  
Output Disable Propagation Delay (High/Low  
to High Impedance)  
Output Enable Propagation Delay (High  
Impedance to High/Low  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity at Logic  
High Output8  
tPHZ, tPLH  
tPZH, tPZL  
6
6
8
8
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
VIx = VDD1 or VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
tR/tF  
|CMH|  
2.5  
35  
ns  
kV/μs  
25  
25  
Common-Mode Transient Immunity at Logic  
Low Output8  
|CML|  
35  
kV/μs  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.2  
Mbps  
Input Dynamic Supply Current per Channel9  
Output Dynamic Supply Current per Channel9  
IDDI (D)  
IDDO (D)  
0.19  
0.05  
mA/Mbps  
mA/Mbps  
1 All voltages are relative to their respective ground.  
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load  
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.  
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through  
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.  
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.  
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.  
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load  
within the recommended operating conditions.  
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of  
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with  
inputs on opposing sides of the isolation barrier.  
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate  
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient  
magnitude is the range over which the common mode is slewed.  
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information  
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current  
for a given data rate.  
Rev. G | Page 5 of 32  
12345678...32

下载PDF

与ADUM1401ARWZ-RL相关器件

型号 品牌 描述 获取价格 数据表
ADUM1401BRW ADI Quad-Channel Digital Isolators

获取价格
ADUM1401BRW-RL ADI SPECIALTY ANALOG CIRCUIT, PDSO16, MS-013AA, SOIC-16

获取价格
ADUM1401BRWZ ADI Quad-Channel Digital Isolators

获取价格
ADUM1401BRWZN ADI Interface Circuit, CMOS, PDSO16

获取价格
ADUM1401BRWZ-RL ADI Quad-Channel Digital Isolators

获取价格
ADUM1401CRW ADI Quad-Channel Digital Isolators

获取价格

与ADUM1401ARWZ-RL相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证