Data Sheet
ADuM1200/ADuM1201
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions /Comments
25 Mbps (CR Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (25)
6.3
3.4
8.0
4.8
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
IDD2 (25)
3.4
6.3
4.8
8.0
mA
mA
12.5 MHz logic signal freq.
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
VIH
VIL
−10
0.7 (VDD1 or VDD2)
+0.01
+10
µA
V
V
V
V
V
V
V
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.3 (VDD1 or VDD2
)
VOAH, VOBH
(VDD1 or VDD2) − 0.1 VDD1 or VDD2
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
0.0
0.04
0.2
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
ADuM1200/ADuM1201AR
Minimum Pulse Width2
Maximum Data Rate3
CL = 15 pF, CMOS signal levels
PW
1000
ns
Mbps
ns
1
50
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL
tPHL, tPLH
PWD
150
40
4
|
ns
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching6
Output Rise/Fall Time (10% to 90%)
ADuM1200/ADuM1201BR
Minimum Pulse Width2
11
10
ps/°C
ns
ns
tPSK
tPSKCD/tPSKOD
tR/tF
50
50
ns
CL = 15 pF, CMOS signal levels
PW
100
ns
Maximum Data Rate3
Propagation Delay4
10
15
Mbps
ns
tPHL, tPLH
PWD
55
3
4
Pulse Width Distortion, |tPLH − tPHL
|
ns
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
5
ps/°C
ns
tPSK
22
tPSKCD
tPSKOD
tR/tF
3
ns
ns
22
3.0
2.5
ns
ns
3 V/5 V Operation
ADuM1200/ADuM1201CR
Minimum Pulse Width2
CL = 15 pF, CMOS signal levels
PW
20
40
ns
Maximum Data Rate3
Propagation Delay4
25
20
50
5
Mbps
ns
tPHL, tPLH
PWD
50
3
4
ns
Pulse Width Distortion, |tPLH − tPHL
|
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching
Codirectional Channels6
Opposing Directional Channels6
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
ps/°C
ns
tPSK
15
tPSKCD
tPSKOD
tR/tF
3
ns
ns
15
3.0
2.5
ns
ns
3 V/5 V Operation
Rev. K | Page 9 of 28