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ADUC7126BSTZ126IRL PDF预览

ADUC7126BSTZ126IRL

更新时间: 2024-02-20 00:07:45
品牌 Logo 应用领域
亚德诺 - ADI 时钟微控制器外围集成电路
页数 文件大小 规格书
110页 1497K
描述
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler

ADUC7126BSTZ126IRL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:ROHS COMPLIANT, MO-026BDD, LQFP-80针数:80
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:1.71
具有ADC:YES地址总线宽度:
位大小:32CPU系列:ARM7
最大时钟频率:41.78 MHzDAC 通道:YES
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:S-PQFP-G80JESD-609代码:e3
长度:12 mm湿度敏感等级:1
I/O 线路数量:40端子数量:80
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP80,.55SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3/3.3 V
认证状态:Not QualifiedRAM(字节):32768
ROM(单词):129024ROM可编程性:FLASH
座面最大高度:1.6 mm速度:41.78 MHz
子类别:Microcontrollers最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:12 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

ADUC7126BSTZ126IRL 数据手册

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Data Sheet  
ADuC7124/ADuC7126  
REVISION HISTORY  
10/14—Rev. C to Rev. D  
Changes to Figure 7 and Table 9 ...................................................14  
Added Figure 8 and Table 10; Renumbered Sequentially..........18  
Change to Figure 17 Caption.........................................................25  
Change to Memory Mapped Registers Section...........................29  
Change to Figure 26........................................................................30  
Changes to Table 18 ........................................................................32  
Changes to Table 21 ........................................................................33  
Changes to Table 22 ........................................................................34  
Moved Table 25................................................................................35  
Change to Table 25..........................................................................35  
Added Table 26................................................................................35  
Change to Table 27..........................................................................36  
Changes to Temperature Sensor Section .....................................42  
Deleted Table 59; Renumbered Sequentially...............................43  
Added Downloading (In-Circuit Programming) via I2  
C Section ..........................................................................................44  
Change to JTAG Access Section and Table 37.............................45  
Changes to Table 45 ........................................................................46  
Changes to RSTCFG Register Section..........................................49  
Deleted Table 72 and Table 75.......................................................49  
Deleted Table 78 ..............................................................................50  
Changes to DAC Section, Table 62, and Table 64.......................51  
Changes to References to ADC and the DACs Setion, Table 66,  
Configuring DAC Buffers in Op Amp Mode Section,  
Change  
To CONVSTART ............................................................. Universal  
CONVSTART  
Changes to Features Section ............................................................1  
Changes to Pin 17 and Pin 30 Descriptions; Table 10................19  
Changes to Flash/EE Memory Section and SRAM Section.......30  
Changes to Table 13 ........................................................................32  
Changes to Flash/EE Memory Section, Programming Section,  
and Serial Downloading (In-Circuit Programming) Section ...46  
Changes to Flash/EE Memory Security Section..........................47  
Changes to Table 56 and Table 57 .................................................50  
Changes to Table 69 ........................................................................56  
Changes to Table 78 ........................................................................60  
Changes to I2C Section ...................................................................72  
Update Table 102.............................................................................73  
Update Table 109.............................................................................76  
Changes to Table 110 ......................................................................77  
Changes to T1CAP Register ..........................................................96  
5/12—Rev. B to Rev. C  
Changed bit to byte in General Description Section....................4  
Changes to Table 2 and Table 3 .......................................................8  
Changes to Table 4 and to Figure 2 and Figure 3..........................9  
Changes to Table 5 and Figure 4....................................................10  
Changes to Table 6 and Figure 5....................................................11  
Changes Table 7 and Figure 6........................................................12  
Changes to Pin 50 and Pin 51 in Table 9......................................14  
Changes to Serial Downloading (In-Circuit Programming)  
Section...............................................................................................44  
Changes to Table 77 ........................................................................59  
Changes to Table 78 ........................................................................58  
Changes to Table 90 ........................................................................60  
Changes to Normal 450 UART Baud Rate Generation  
Section...............................................................................................61  
Changes to Serial Peripheral Interface Section ...........................66  
Added equation to Timers Section and added Hr: Min: Sec  
1/128 Format Section......................................................................91  
Changes to Figure 69 ................................................................... 103  
Updated Outline Dimensions..................................................... 104  
Changes to Ordering Guide........................................................ 105  
DACBCFG Register Section, and Table 67..................................52  
Added DACBKEY1 Register Section and DACBKEY2 Register  
Section ..............................................................................................53  
Changes to Table 69 and Figure 45 ...............................................54  
Changes to and External Crystal Selection and External Clock  
Selection ...........................................................................................55  
Changes to PLLCON Register and POWCON0 Register  
Section ..............................................................................................56  
Changes to Table 78 ........................................................................58  
Changes to Table 81 ........................................................................59  
Changes to Table 84 and Table 90.................................................60  
Changes to Table 93, COM0FCR Register Section, COM1FCR  
Register Section, and Table 94.......................................................63  
Changes to Serial Peripheral Interface Section ...........................66  
Change to SPI Registers Section....................................................67  
Changes to SPIDIV Register Section and Table 101 ..................68  
Change to I2C Master Transmit Register Section .......................73  
Change to Table 109........................................................................74  
Change to I2C Slave Status Registers Section...............................75  
Change to Table 113........................................................................79  
Changes to Table 114 Title and Figure 50....................................80  
Change to IRQCLRE Register Register .......................................90  
Change to Figure 54........................................................................92  
Changes to Table 141, T1CLRI Register Section, and T1CAP  
Register Section ...............................................................................93  
Changes to Table 143 ......................................................................94  
Added External Memory Interfacting Section, Table 145,  
1/11—Rev A to Rev B  
Changes to Table 1 ............................................................................5  
10/10—Rev. 0 to Rev. A  
Added ADuC7126..............................................................Universal  
Changes to Features Section ............................................................1  
Moved Figure 1..................................................................................1  
Changes to Figure 1...........................................................................1  
Changes to General Description Section .......................................4  
Changes to Voltage Output at 25°C, Voltage TC, IOVDD Current  
in Active Mode, and IOVDD Current in Pause Mode Parameters,  
Table 1 .................................................................................................5  
Change to Table 8 ............................................................................13  
Changed REFGND to GNDREF ......................................................13  
Table 146, and Figure 57.................................................................96  
Rev. D | Page 3 of 110  
 

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