ꢁT75C
C
TIMING SPECIFICATIONS AND DIAGRAM
Measure the SDA and SCL timing with the input filters turned on to meet the fast mode I2C specification. Switching off the input filters
improves the transfer rate but has a negative affect on the EMC behavior of the part.
TA = TMIN to TMAX, VDD = +2.7 V to +5.5 V, unless otherwise noted.
Table 3.
Parameter1
MIN
2.5
50
0
0
50
50
TYP
MAX
Units
μs
ns
ns
μs
ns
ns
ns
ns
Comments
Serial Clock Period, t1
Fast mode I2C. See Figure 2
Data In Setup Time to SCL High, t2
Data Out Stable After SCL Low, t3
Data Out Stable After SCL Low, t3
SDA Low Setup Time to SCL Low (Start Condition), t4
SDA High Hold Time After SCL High (Stop Condition), t5
SDA and SCL Rise Time, t6
SDA and SCL Rise Time, t6
SDA and SCL Fall Time, t7
Capacitive Load for each Bus Line, CB
See Figure 2
0.92
3.452
Fast mode I2C. See Figure 2
Standard mode I2C. See Figure 2
See Figure 2
See Figure 2
300
1000
300
400
Fast mode I2C. See Figure 2
Standard mode I2C. See Figure 2
See Figure 2
ns
pF
1 Guaranteed by design and characterization; not production tested.
2 This time has to be met only if the master does not stretch the low period of the SCL signal.
t1
SCL
t5
t2
t4
SDA
DATA IN
t3
SDA
DATA OUT
t7
t6
Figure 2. SMBus/I2C Timing Diagram
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