ADT7516/ADT7517/ADT7519
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
ON-CHIP REFERENCE
Reference Voltage
4
2.28
80
V
Temperature Coefficient4
ppm/°C
OUTPUT CHARACTERISTICS
4
Output Voltage 6
0.001
VDD − 0.1
V
This is a measure of the minimum and maximum
drive capability of the output amplifier.
DC Output Impedance
Short Circuit Current
0.5
25
16
2.5
5
Ω
mA
mA
µs
VDD = 5 V.
VDD = 3 V.
Power-Up Time
Coming out of power-down mode. VDD = 5 V.
Coming out of power-down mode. VDD = 3.3 V.
µs
DIGITAL INPUTS
4
Input Current
1
0.8
µA
V
V
pF
ns
VIN = 0 V to VDD.
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
1.89
3
10
50
All digital inputs.
Input filtering suppresses noise spikes of less
than 50 ns.
SCL, SDA Glitch Rejection
LDAC Pulse Width
20
ns
Edge triggered input.
DIGITAL OUTPUT
Digital High Voltage, VOH
Output Low Voltage, VOL
Output High Current, IOH
Output Capacitance, COUT
INT/INT Output Saturation Voltage
2.4
V
V
mA
pF
V
ISOURCE = ISINK = 200 µA.
IOL = 3 mA.
VOH = 5 V.
0.4
1
50
0.8
I
OUT = 4 mA.
I2C TIMING CHARACTERISTICS 7, 8
Serial Clock Period, t1
Data In Setup Time to SCL High, t2
Data Out Stable after SCL Low, t3
SDA Low Setup Time to SCL
Low (Start Condition), t4
2.5
50
0
µs
ns
ns
ns
Fast Mode I2C. See Figure 2.
See Figure 2.
See Figure 2.
50
SDA High Hold Time after SCL
High (Stop Condition), t5
50
ns
ns
See Figure 2.
See Figure 2.
SDA and SCL Fall Time, t6
90
35
, 9
SPI TIMING CHARACTERISTICS
CS to SCLK Setup Time, t1
SCLK High Pulse Width, t2
SCLK Low Pulse Width, t3
4
0
ns
ns
ns
ns
See Figure 3.
See Figure 3.
See Figure 3.
50
50
Data Access Time after SCLK
Falling Edge, t4, 10
Data Setup Time Prior to SCLK
Rising Edge, t5
20
0
ns
ns
See Figure 3.
See Figure 3.
Data Hold Time after SCLK Rising
Edge, t6
CS to SCLK Hold Time, t7
0
µs
ns
See Figure 3.
See Figure 3.
CS to DOUT High Impedance, t8
40
Rev. A | Page 5 of 44