Datasheet > ADT7519_15

ADT7519_15

更新时间： 2022-02-26 12:22:37

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
44页	3247K
描述
SPI-/IC-Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output

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ADT7519_15 数据手册

ADT7516/ADT7517/ADT7519

Parameter¹

Min

Typ

Max

Unit

Conditions/Comments

ON-CHIP REFERENCE

Reference Voltage⁴

Temperature Coefficient⁴

OUTPUT CHARACTERISTICS⁴

Output Voltage⁶

2.2662 2.28

2.2938

ppm/°C

0.001

V_DD− 0.1

This is a measure of the minimum and maximum

drive capability of the output amplifier

DC Output Impedance

Short Circuit Current

0.5

2.5

μs

V_DD= 5 V

V_DD= 3 V

Power-Up Time

Coming out of power-down mode, V_DD= 5 V

Coming out of power-down mode, V_DD= 3.3 V

μs

DIGITAL INPUTS⁴

Input Current

0.8

μA

V_IN= 0 V to V_DD

V_IL, Input Low Voltage

V_IH, Input High Voltage

Pin Capacitance

1.89

All digital inputs

Input filtering suppresses noise spikes of less

than 50 ns

SCL, SDA Glitch Rejection

LDAC Pulse Width

Edge triggered input

DIGITAL OUTPUT

Digital High Voltage, V_OH

Output Low Voltage, V_OL

Output High Current, I_OH

Output Capacitance, C_OUT

INT/INT Output Saturation Voltage

2.4

I_SOURCE= I_SINK= 200 μA

I_OL= 3 mA

V_OH= 5 V

0.4

0.8

I_OUT= 4 mA

I²C TIMING CHARACTERISTICS^7,

Serial Clock Period, t₁

Data In Setup Time to SCL High, t₂

Data Out Stable after SCL Low, t₃

SDA Low Setup Time to SCL

Low (Start Condition), t₄

2.5

μs

Fast mode I²C, see Figure 2

See Figure 2

SDA High Hold Time after SCL

High (Stop Condition), t₅

See Figure 2

SDA and SCL Fall Time, t₆

SDA and SCL Rise Time, t₇

SPI TIMING CHARACTERISTICS^{4, 10}

CS to SCLK Setup Time, t₁

SCLK High Pulse Width, t₂

SCLK Low Pulse Width, t₃

Data Access Time after SCLK

300

See Figure 2

300⁹

See Figure 3

Falling Edge, t₄

Data Setup Time Prior to SCLK

Rising Edge, t₅

Data Hold Time after SCLK

Rising Edge, t₆

See Figure 3

CS to SCLK Hold Time, t₇

μs

See Figure 3

CS to DOUT High Impedance, t₈

POWER REQUIREMENTS

V_DD

V_DDSettling Time

I_DD(Normal Mode)¹²

2.7

5.5

V_DDsettles to within 10% of its final voltage level

V_DD= 3.3 V, V_IH= V_DD, and V_IL= GND

V_DD= 5 V, V_IH= V_DD, and V_IL= GND

2.2

Rev. B | Page 5 of 44

1 2 3 456 7 8...44

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