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ADT7316ARQZ-REEL7 PDF预览

ADT7316ARQZ-REEL7

更新时间： 2024-01-24 12:44:24
品牌 Logo 应用领域
亚德诺 - ADI 传感器换能器温度传感器输出元件
页数 文件大小 规格书
44页 3873K
描述
Accurate Digital Temperature Sensor

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ADT7316ARQZ-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：SSOP16,.25
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：0.81最大精度（摄氏度）：5 Cel
主体宽度：3.9 mm主体高度：1.54 mm
主体长度或直径：4.9 mm外壳：PLASTIC
JESD-609代码：e3安装特点：SURFACE MOUNT
位数：12端子数量：16
最大工作电流：0.001 mA最高工作温度：120 °C
最低工作温度：-40 °C输出接口类型：4-WIRE INTERFACE
封装主体材料：PLASTIC/EPOXY封装等效代码：SSOP16,.25
封装形状/形式：RECTANGULAR电源：3/5 V
传感器/换能器类型：TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL子类别：Other Sensors
最大供电电压：5.5 V最小供电电压：2.7 V
表面贴装：YES技术：CMOS
端子面层：Matte Tin (Sn)端接类型：SOLDER
Base Number Matches：1

ADT7316ARQZ-REEL7 数据手册

 浏览型号ADT7316ARQZ-REEL7的Datasheet PDF文件第2页浏览型号ADT7316ARQZ-REEL7的Datasheet PDF文件第3页浏览型号ADT7316ARQZ-REEL7的Datasheet PDF文件第4页浏览型号ADT7316ARQZ-REEL7的Datasheet PDF文件第6页浏览型号ADT7316ARQZ-REEL7的Datasheet PDF文件第7页浏览型号ADT7316ARQZ-REEL7的Datasheet PDF文件第8页 
ADT7316/ADT7317/ADT7318  
Parameter1  
Min  
Typ  
Max  
Unit  
Conditions/Comments  
DIGITAL OUTPUT  
Output High Voltage, VOH  
Output Low Voltage, VOL  
Output High Current, IOH  
Output Capacitance, COUT  
2.4  
V
V
mA  
pF  
V
ISOURCE = ISINK = 200 μA.  
IOL = 3 mA.  
VOH = 5 V.  
0.4  
1
50  
0.8  
INT  
INT/  
IOUT = 4 mA.  
Output Saturation Voltage  
I2C TIMING CHARACTERISTICS7, 8  
Serial Clock Period, t1  
Fast-mode I2C. See Figure 4.  
2.5  
50  
0
μs  
ns  
ns  
ns  
Data In Setup Time to SCL High, t2  
Data Out Stable After SCL Low, t3  
See Figure 4.  
See Figure 4.  
SDA Low Setup Time to SCL Low  
(Start Condition), t4  
50  
SDA High Hold Time After SCL High 50  
(Stop Condition), t5  
ns  
See Figure 4.  
SDA and SCL Fall Time, t6  
300  
3009  
ns  
ns  
See Figure 4.  
See Figure 4.  
SDA and SCL Rise Time, t6  
SPI TIMING CHARACTERISTICS10, 11  
CS  
0
ns  
ns  
ns  
ns  
to SCLK Setup Time, t1  
See Figure 7.  
See Figure 7.  
See Figure 7.  
See Figure 7.  
SCLK High Pulse Width, t2  
50  
50  
SCLK Low Pulse Width, t3  
Data Access Time After SCLK Falling  
Edge, t4  
Data Setup Time Prior to SCLK  
Rising Edge, t5  
Data Hold Time after SCLK Rising  
Edge, t6  
35  
40  
12  
20  
0
ns  
ns  
See Figure 7.  
See Figure 7.  
CS  
CS  
0
ns  
ns  
to SCLK Hold Time, t7  
See Figure 7.  
See Figure 7.  
to DOUT High Impedance, t8  
POWER REQUIREMENTS  
VDD  
VDD Settling Time  
IDD (Normal Mode)13  
2.7  
5.5  
50  
3
V
ms  
mA  
mA  
μA  
μA  
mW  
μW  
VDD settles to within 10% of its final voltage level.  
VDD = 3.3 V, VIH = VDD, and VIL = GND.  
VDD = 5 V, VIH = VDD , and VIL = GND.  
VDD = 3.3 V, VIH = VDD, and VIL = GND.  
VDD = 5 V, VIH = VDD, and VIL = GND.  
VDD = 3.3 V, using normal mode.  
2.2  
3
IDD (Power-Down Mode)  
Power Dissipation  
10  
10  
10  
33  
VDD = 3.3 V, using shutdown mode.  
1 See the Terminology section.  
2 DC specifications tested with the outputs unloaded.  
3 Linearity is tested using a reduced code range: ADT7316 (Code 115 to 4095); ADT7317 (Code 28 to 1023); ADT7318 (Code 8 to 255).  
4 A round robin is the continuous sequential measurement of the following three channels: VDD, internal temperature, and external temperature.  
5 Guaranteed by design and characterization, but not production tested.  
6 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD, offset plus  
gain error must be positive.  
7 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate,  
but has a negative effect on the EMC behavior of the part.  
8 Guaranteed by design. Not tested in production.  
9 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.  
10 Guaranteed by design and characterization, but not production tested.  
11 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.  
12 Measured with the load circuit of Figure 5.  
13  
I
specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.  
DD  
Rev. B | Page 5 of 44  
 
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