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ADT7301-5ARM PDF预览

ADT7301-5ARM

更新时间: 2022-12-01 22:57:33
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
10页 113K
描述
IC,TEMPERATURE SENSOR,CMOS,TSSOP,8PIN,PLASTIC

ADT7301-5ARM 数据手册

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ADT7301  
ABSO LU T E M AXIM U M RAT IN G S1  
Preliminary Technical Data  
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V  
Digital Input Voltage to GND . . . . . . . 0.3 V to VDD + 0.3 V  
Digital Output Voltage to GND . . . . . 0.3 V to VDD + 0.3 V  
Operating T emperature Range2 . . . . . 40°C to +150°C  
Storage T emperature Range . . . . . . . . 65°C to +150°C  
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . +150°C  
6-Lead SOT -23 (RJ-6) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Power D issipation3 . . . . . . . WMAX = (TJMAX - TA4)/θJA  
T hermal Impedance  
I
200A  
OL  
TO  
OUTPUT  
PIN  
+1.6V  
C
L
50pF  
200A  
I
OH  
θ
JA, Junction-to-Ambient (still air) . . . 190.4°C /W  
8-Lead M SOP (RM -8) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Power D issipation3 . . . . . . . WMAX = (TJMAX - TA4)/θJA  
T hermal Impedance5  
Figure 1. Load Circuit for Data Access Tim e and Bus  
Relinquish Tim e  
θJA, Junction-to-Ambient (still air) . . . 205.9°C /W  
θ
JC , Junction-to-C ase . . . . . . . . . . . . . . 43.74°C /W  
IR Reflow Soldering  
Peak T emperature . . . . . . . . . . . . +220°C (-0/+5°C)  
T ime at Peak T emperature . . . . . . . . . . 10 to 20 secs  
Ramp-up Rate . . . . . . . . . . . . . . . . . . . . . . . 2-3°C /sec  
Ramp-down Rate . . . . . . . . . . . . . . . . . . . . . . -6°C /sec  
1.2  
1
1
Stresses above those listed under Absolute M axim um Ratings m ay  
0.8  
cause permanent damage to the device. T his is  
a stress rating only;  
functional operation of the device at these or any other conditions above  
those indicated in the operational section of this specification is not  
im plied . Exposu re to absolu te m axim u m ratin g con d ition s for ex-  
tended periods may affect device reliability.  
SOT-23  
0.6  
MSOP  
2
3
It is not recommended to operate the device at temperatures above  
0.4  
+125°C for greater than  
a total of 5% of the lifetime of the device. Any  
exposure beyond this limit will affect device reliability.  
Values relate to package being used on a standard 2-layer pcb. Reference  
0.2  
0
Figure 2. for  
(T A).  
a plot of max power dissipation vs. ambient temperature  
4T A  
5Junction-to-C ase resistance is applicable to com ponents featuring  
preferential flow direction, eg. components mounted on heat sink.  
= Am bient T em perature.  
-40 -30 -20 -10  
0
10 20 30 40 50 60 70  
80 90 100 110 120 125 130 140 150  
Temperature - °C  
a
a
Ju n ction -to-Am bien t resistan ce is m ore u sefu l for air-cooled P C B-  
m ou n ted com pon en ts.  
Figure 2. Plot of Maxim um Power Dissipation vs. Tem -  
perature  
TIMING CHARACTERISTICS1, 2, 3  
(T = TMIN to T , V = +2.7 V to +5.5 V, unless otherwise noted)  
A
MAX DD  
Parameter  
Lim it  
U nits  
C omments  
t1  
t2  
t3  
0
ns min  
ns min  
ns min  
ns max  
CS to SCLK Setup T ime  
25  
25  
35  
SCLK H igh Pulsewidth  
SCLK Low Pulsewidth  
4
t4  
Data Access T ime After SCLK Falling Edge  
t5  
t6  
t7  
20  
0
ns min  
ns min  
ns min  
ns max  
Data Setup T ime Prior to SCLK Rising Edge  
Data H old T ime After SCLK Rising Edge  
CS to SCLK H old T ime  
0
40  
4
t8  
CS to DOUT H igh Impedance  
N O T E S  
1G uaranteed by design and characterization, not production tested.  
2All input signals are specified with tr  
3See F igure 2.  
= tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.  
4M easured with the load circuit of Figure 1.  
4 –  
REV. PrE  

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