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ADSP-2183KSTZ-115 PDF预览

ADSP-2183KSTZ-115

更新时间： 2024-01-03 06:03:15
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 时钟外围集成电路
页数 文件大小 规格书
32页 935K
描述
24-BIT, 14.4 MHz, OTHER DSP, PQFP128, METRIC, PLASTIC, TQFP-128

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ADSP-2183KSTZ-115 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP,针数：128
Reach Compliance Code：unknown风险等级：5.82
地址总线宽度：14桶式移位器：YES
边界扫描：NO最大时钟频率：14.4 MHz
外部数据总线宽度：24格式：FIXED POINT
内部总线架构：MULTIPLEJESD-30 代码：R-PQFP-G128
JESD-609代码：e3长度：20 mm
低功率模式：YES湿度敏感等级：3
端子数量：128最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：1.6 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER

ADSP-2183KSTZ-115 数据手册

 浏览型号ADSP-2183KSTZ-115的Datasheet PDF文件第1页浏览型号ADSP-2183KSTZ-115的Datasheet PDF文件第2页浏览型号ADSP-2183KSTZ-115的Datasheet PDF文件第3页浏览型号ADSP-2183KSTZ-115的Datasheet PDF文件第5页浏览型号ADSP-2183KSTZ-115的Datasheet PDF文件第6页浏览型号ADSP-2183KSTZ-115的Datasheet PDF文件第7页 
ADSP-2183  
In addition to the address and data bus for external memory  
connection, the ADSP-2183 has a 16-bit Internal DMA port  
(IDMA port) for connection to external systems. The IDMA  
port is made up of 16 data/address pins and five control pins.  
The IDMA port provides transparent, direct access to the DSPs  
on-chip program and data RAM.  
The ADSP-2183 provides up to 13 general-purpose flag pins.  
The data input and output pins on SPORT1 can be alternatively  
configured as an input flag and an output flag. In addition, eight  
flags are programmable as inputs or outputs and three flags are  
always outputs.  
A programmable interval timer generates periodic interrupts. A  
16-bit count register (TCOUNT) is decremented every n pro-  
cessor cycle, where n is a scaling value stored in an 8-bit register  
(TSCALE). When the value of the count register reaches zero,  
an interrupt is generated and the count register is reloaded from  
a 16-bit period register (TPERIOD).  
An interface to low cost byte-wide memory is provided by the  
Byte DMA port (BDMA port). The BDMA port is bidirectional  
and can directly address up to four megabytes of external RAM  
or ROM for off-chip storage of program overlays or data tables.  
The byte memory and I/O memory space interface supports  
slow memories and I/O memory-mapped peripherals with pro-  
grammable wait state generation. External devices can gain  
control of external buses with bus request/grant signals (BR,  
BGH and BG). One execution mode (Go Mode) allows the  
ADSP-2183 to continue running from on-chip memory. Normal  
execution mode requires the processor to halt while buses are  
granted.  
Serial Ports  
The ADSP-2183 incorporates two complete synchronous serial  
ports (SPORT0 and SPORT1) for serial communications and  
multiprocessor communication.  
Here is a brief list of the capabilities of the ADSP-2183  
SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third  
Edition, for further details.  
The ADSP-2183 can respond to thirteen possible interrupts,  
eleven of which are accessible at any given time. There can be  
up to six external interrupts (one edge-sensitive, two level-  
sensitive and three configurable) and seven internal interrupts  
generated by the timer, the serial ports (SPORTs), the Byte  
DMA port and the power-down circuitry. There is also a master  
RESET signal.  
• SPORTs are bidirectional and have a separate, double-  
buffered transmit and receive section.  
• SPORTs can use an external serial clock or generate their  
own serial clock internally.  
• SPORTs have independent framing for the receive and trans-  
mit sections. Sections run in a frameless mode or with frame  
synchronization signals, internally or externally generated.  
Frame sync signals are active high or inverted, with either of  
two pulsewidths and timings.  
The two serial ports provide a complete synchronous serial inter-  
face with optional companding in hardware and a wide variety of  
framed or frameless data transmit and receive modes of operation.  
Each port can generate an internal programmable serial clock or  
accept an external serial clock.  
21xx CORE  
ADSP-2183 INTEGRATION  
2
POWER  
DOWN  
CONTROL  
LOGIC  
PROGRAM  
SRAM  
DATA  
SRAM  
16k
؋
16  
INSTRUCTION  
REGISTER  
8
16k
؋
24  
PROGRAMMABLE  
I/O  
BYTE  
DMA  
CONTROLLER  
DATA  
ADDRESS  
GENERATOR  
#2  
DATA  
ADDRESS  
GENERATOR  
#1  
3
PROGRAM  
FLAGS  
SEQUENCER  
PMA BUS  
DMA BUS  
14  
14  
PMA BUS  
14  
MUX  
DMA BUS  
EXTERNAL  
ADDRESS  
BUS  
PMD BUS  
24  
PMD BUS  
EXTERNAL  
DATA  
BUS  
BUS  
MUX  
EXCHANGE  
DMD  
BUS  
DMD BUS  
24  
16  
IN  
P
U
T
R
E
G
S
INPUT REGS  
SHIFTER  
INPUT REGS  
COMPANDING  
CIRCUITRY  
16  
INTERNAL  
DMA  
PORT  
ALU  
MAC  
TIMER  
TRANSMIT REG  
TRANSMIT REG  
OUTPUT REGS  
OUTPUT REGS  
OUTPUT REGS  
RECEIVE REG  
RECEIVE REG  
4
SERIAL  
PORT 0  
SERIAL  
PORT 0  
16  
INTERRUPTS  
R BUS  
5
5
Figure 1. Block Diagram  
–3–  
REV. C  
1234567...32

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