Datasheet > 微控制器和处理器 > 数字信号处理器> ADSP-21369BBP-2A

ADSP-21369BBP-2A

更新时间： 2024-01-10 11:04:51

品牌	Logo	应用领域
亚德诺 - ADI		微控制器和处理器外围集成电路数字信号处理器时钟
页数	文件大小	规格书
56页	1696K
描述
SHARC Processors

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数据手册

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ADSP-21369BBP-2A 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA,	针数：	256
Reach Compliance Code：	unknown	风险等级：	5.72
其他特性：	ALSO REQUIRES 3.3V SUPPLY	地址总线宽度：	24
桶式移位器：	YES	边界扫描：	YES
最大时钟频率：	55.56 MHz	外部数据总线宽度：	32
格式：	FLOATING POINT	内部总线架构：	MULTIPLE
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
长度：	27 mm	低功率模式：	NO
湿度敏感等级：	3	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	225	认证状态：	COMMERCIAL
座面最大高度：	1.7 mm	最大供电电压：	1.26 V
最小供电电压：	1.14 V	标称供电电压：	1.2 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	27 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

ADSP-21369BBP-2A 数据手册

ADSP-21367/ADSP-21368/ADSP-21369

Table 2. Internal Memory Space ¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Instruction Word (48 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

BLOCK 0 ROM (Reserved)

0x0004 0000–0x0004 BFFF

BLOCK 0 ROM (Reserved)

0x0008 0000–0x0008 FFFF

BLOCK 0 ROM (Reserved)

0x0008 0000–0x0009 7FFF

BLOCK 0 ROM (Reserved)

0x0010 0000–0x0012 FFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 4000–0x0009 FFFF

0x0009 E000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

BLOCK 0 SRAM

0x0004 C000–0x0004 EFFF

0x0009 0000–0x0009 3FFF

0x0009 8000–0x0009 DFFF

0x0013 0000–0x0013 BFFF

BLOCK 1 ROM (Reserved)

0x0005 0000–0x0005 BFFF

BLOCK 1 ROM (Reserved)

0x000A 0000–0x000A FFFF

BLOCK 1 ROM (Reserved)

0x000A 0000–0x000B 7FFF

BLOCK 1 ROM (Reserved)

0x0014 0000–0x0016 FFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B FFFF

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

BLOCK 1 SRAM

0x0005 C000–0x0005 EFFF

0x000B 0000–0x000B 3FFF

0x000B 8000–0x000B DFFF

0x0017 0000–0x0017 BFFF

BLOCK 2 SRAM

0x0006 0000–0x0006 0FFF

0x000C 0000–0x000C 1554

0x000C 0000–0x000C 1FFF

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000– 0x0006 FFFF

0x000C 1555–0x000C 3FFF

0x000C 2000–0x000D FFFF

0x0018 4000–0x001B FFFF

BLOCK 3 SRAM

0x0007 0000–0x0007 0FFF

0x000E 0000–0x000E 1554

0x000E 0000–0x000E 1FFF

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000–0x0007 FFFF

0x000E 1555–0x000F FFFF

0x000E 2000–0x000F FFFF

0x001C 4000–0x001F FFFF

¹The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.

The controller maintains all of the memory banks as a contigu-

ous address space so that the processor sees this as a single

address space, even if different size devices are used in the

different banks.

Table 4. External Memory for SDRAM Addresses

Size in

Bank

Words

Address Range

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as either 32 bits wide for max-

imum performance and bandwidth or 16 bits wide for

minimum device count and lower system cost.

Bank 0

Bank 1

Bank 2

Bank 3

62M

0x0020 0000 – 0x03FF FFFF

0x0400 0000 – 0x07FF FFFF

0x0800 0000 – 0x0BFF FFFF

0x0C00 0000 – 0x0FFF FFFF

64M

The SDRAM controller address, data, clock, and control pins

can drive loads up to 30 pF. For larger memory systems, the

SDRAM controller external buffer timing should be selected

and external buffering should be provided so that the load on

the SDRAM controller pins does not exceed 30 pF.

Asynchronous Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory con-

trol lines. Bank 0 occupies a 14M word window and banks 1, 2,

and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of

interfacing to a range of memories and I/O devices tailored

either to high performance or to low cost and power.

Table 3. External Memory for NonSDRAM Addresses

Size in

Bank

Words

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

14M

0x0020 0000 – 0x00FF FFFF

0x0400 0000 – 0x04FF FFFF

0x0800 0000 – 0x08FF FFFF

0x0C00 0000 – 0x0CFF FFFF

16M

Rev. A

Page 6 of 56

August 2006

1...3 4 567 8 9...56

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与ADSP-21369BBP-2A相关器件

型号	品牌	描述	获取价格	数据表
ADSP-21369BBPZ-2A	ADI	SHARC Processors	获取价格
ADSP-21369BSWZ-1A	ADI	SHARC Processors	获取价格
ADSP-21369BSWZ-2A	ADI	SHARC Processors	获取价格
ADSP-21369KBP-2A	ADI	SHARC Processors	获取价格
ADSP-21369KBP-3A	ADI	IC 0-BIT, 25 MHz, OTHER DSP, PBGA256, SBGA-256, Digital Signal Processor	获取价格
ADSP-21369KBP-ENG	ADI	IC 32-BIT, 66.66 MHz, OTHER DSP, PBGA256, MO-192-BAL-2, SBGA-256, Digital Signal Processor	获取价格

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