ADSP-21367/ADSP-21368/ADSP-21369
The asynchronous memory controller is capable of a maximum
throughput of 264M bytes/s using a 66 MHz external bus speed.
Other features include 8-bit to 32-bit and 16-bit to 32-bit pack-
ing and unpacking, booting from bank select 1, and support for
delay line DMA.
the SPI interface, two for the external port, and two for
memory-to-memory transfers. Programs can be downloaded to
the processors using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
Delay Line DMA
Shared External Memory
The ADSP-21367/ADSP-21368/ADSP-21369 processors pro-
vide delay line DMA functionality. This allows processor reads
and writes to external delay line buffers (in external memory,
SRAM, or SDRAM) with limited core interaction.
The ADSP-21368 processor supports connecting to common
shared external memory with other ADSP-21368 processors to
create shared external bus processor systems. This support
includes:
• Distributed, on-chip arbitration for the shared external bus
• Fixed and rotating priority bus arbitration
• Bus time-out logic
Digital Audio and Digital Peripheral Interfaces (DAI/DPI)
The digital audio and digital periphal interfaces (DAI and DPI)
provide the ability to connect various peripherals to any of the
DSP’s DAI or DPI pins (DAI_P20–1 and DPI_P14–1).
• Bus lock
Programs make these connections using the signal routing units
(SRU1 and SRU2), shown in Figure 1.
Multiple processors can share the external bus with no addi-
tional arbitration logic. Arbitration logic is included on-chip to
allow the connection of up to four processors.
The SRUs are matrix routing units (or group of multiplexers)
that enable the peripherals provided by the DAI and DPI to be
interconnected under software control. This allows easy use of
the associated peripherals for a much wider variety of applica-
tions by using a larger set of algorithms than is possible with
nonconfigurable signal paths.
Bus arbitration is accomplished through the BR1-4 signals and
the priority scheme for bus arbitration is determined by the set-
ting of the RPBA pin. Table 5 on Page 12 provides descriptions
of the pins used in multiprocessor systems.
INPUT/OUTPUT FEATURES
The DAI and DPI also include eight serial ports, an S/PDIF
receiver/transmitter, four precision clock generators (PCG),
eight channels of synchronous sample rate converters, and an
input data port (IDP). The IDP provides an additional input
path to the processor core, configurable as either eight channels
of I2S serial data or as seven channels plus a single 20-bit wide
synchronous parallel data acquisition port. Each data channel
has its own DMA channel that is independent from the proces-
sor’s serial ports.
The I/O processor provides 34 channels of DMA, as well as an
extensive set of peripherals. These include a 20-pin digital audio
interface which controls:
• Eight serial ports
• S/PDIF receiver/transmitter
• Four precision clock generators
• Four stereo sample rate converters
• Internal data port/parallel data acquisition port
For complete information on using the DAI and DPI, see the
ADSP-21368 SHARC Processor Hardware Reference.
The processors also contain a 14-pin digital peripheral interface
which controls:
Serial Ports
The processors feature eight synchronous serial ports (SPORTs)
that provide an inexpensive interface to a wide variety of digital
and mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
• Three general-purpose timers
• Two serial peripheral interfaces
• Two universal asynchronous receiver/transmitters
(UARTs)
• A two-wire interface (I2C-compatible)
DMA Controller
Serial ports are enabled via 16 programmable and simultaneous
receive or transmit pins that support up to 32 transmit or 32
receive channels of audio data when all eight SPORTS are
enabled, or eight full duplex TDM streams of 128 channels
per frame.
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the processor’s internal memory and its serial ports, the
SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP), or
the UART. Thirty-four channels of DMA are available on the
ADSP-21367/ADSP-21368/ADSP-21369—16 via the serial
ports, eight via the input data port, four for the UARTs, two for
The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Rev. A
|
Page 7 of 56
|
August 2006
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