ADSP-21160M/ADSP-21160N
GENERAL DESCRIPTION
The ADSP-21160x SHARC® DSP family has two members:
ADSP-21160M and ADSP-21160N. The ADSP-21160M is fabri-
cated in a 0.25 micron CMOS process. The ADSP-21160N is
fabricated in a 0.18 micron CMOS process. The ADSP-21160N
offers higher performance and lower power consumption than
the ADSP-21160M. Easing portability, the ADSP-21160x is
application source code compatible with first generation
ADSP-2106x SHARC DSPs in SISD (single instruction, single
data) mode. To take advantage of the processor’s SIMD (single-
instruction, multiple-data) capability, some code changes are
needed. Like other SHARC DSPs, the ADSP-21160x is a 32-bit
processor that is optimized for high performance DSP applica-
tions. The ADSP-21160x includes a core running up to
100 MHz, a dual-ported on-chip SRAM, an integrated I/O pro-
cessor with multiprocessing support, and multiple internal
buses to eliminate I/O bottlenecks.
Table 2. ADSP-21160x Benchmarks
ADSP-21160M ADSP-21160N
Benchmark Algorithm
80 MHz 100 MHz
1024 Point Complex FFT
(Radix 4, with reversal)
115 μs 92 μs
FIR Filter (per tap)
6.25 ns
25 ns
5 ns
IIR Filter (per biquad)
20 ns
Matrix Multiply (pipelined)
[33] [31]
[44] [41]
56.25 ns
100 ns
45 ns
80 ns
Divide (y/x)
37.5 ns
30 ns
Inverse Square Root
DMA Transfer Rate
56.25 ns
560M bytes/s
45 ns
800M bytes/s
Table 1 shows major differences between the ADSP-21160M
and ADSP-21160N processors.
The functional block diagram (Figure 1 on Page 1) of the
ADSP-21160x illustrates the following architectural features:
• Two processing elements, each made up of an ALU, multi-
plier, shifter, and data register file
Table 1. ADSP-21160x SHARC Processor Family Features
Feature
ADSP-21160M
ADSP-21160N
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
SRAM
4 Mbits
4 Mbits
Operating Voltage
3.3 V I/O
2.5 V Core
3.3 V I/O
1.9 V Core
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core proces-
sor cycle
Instruction Rate
80 MHz
100 MHz
Link Port Transfer Rate (6)
80 MBytes/s
100 MBytes/s
50 Mbits/s
• Interval timer
Serial Port Transfer Rate (2) 40 Mbits/s
• On-chip SRAM (4M bits)
• External port that supports:
• Interfacing to off-chip memory peripherals
The ADSP-21160x introduces single-instruction, multiple-data
(SIMD) processing. Using two computational units
(ADSP-2106x SHARC DSPs have one), the ADSP-21160x can
double performance versus the ADSP-2106x on a range of DSP
algorithms.
• Glueless multiprocessing support for six
ADSP-21160x SHARC DSPs
• Host port
Fabricated in a state-of-the-art, high speed, low power CMOS
process, the ADSP-21160N has a 10 ns instruction cycle time.
With its SIMD computational hardware running at 100 MHz,
the ADSP-21160N can perform 600 million math operations
per second (480 million operations for ADSP-21160M at a
12.5 ns instruction cycle time).
• DMA controller
• Serial ports and link ports
• JTAG test access port
Figure 2 shows a typical single-processor system. A multipro-
cessing system appears in Figure 3 on Page 6.
Table 2 shows performance benchmarks for the ADSP-21160x.
ADSP-21160X FAMILY CORE ARCHITECTURE
These benchmarks provide single-channel extrapolations of
measured dual-channel (SIMD) processing performance. For
more information on benchmarking and optimizing DSP code
for single- and dual-channel processing, see the Analog Devices
website (www.analog.com).
The ADSP-21160x processor includes the following architec-
tural features of the ADSP-2116x family core. The
ADSP-21160x is code compatible at the assembly level with the
ADSP-2106x and ADSP-21161.
The ADSP-21160x continues the SHARC family’s industry-
leading standards of integration for DSPs, combining a high
performance 32-bit DSP core with integrated, on-chip system
features. These features include a 4M-bit dual-ported SRAM
memory, host processor interface, I/O processor that supports
14 DMA channels, two serial ports, six link ports, external par-
allel bus, and glueless multiprocessing.
SIMD Computational Engine
The ADSP-21160x contains two computational processing ele-
ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and
PEY, and each contains an ALU, multiplier, shifter, and register
file. PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
Rev. C
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Page 4 of 60
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February 2013
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