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ADSP-2103KP-40

更新时间： 2024-01-17 13:33:41
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器装置计算机时钟
页数 文件大小 规格书
64页 666K
描述
ADSP-2100 Family DSP Microcomputers

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ADSP-2103KP-40 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：LCC
包装说明：QCCJ,针数：68
Reach Compliance Code：unknown风险等级：5.78
其他特性：20 MIPS; SINGLE CYCLE INSTRUCTION EXECUTION地址总线宽度：14
桶式移位器：YES边界扫描：NO
最大时钟频率：10.24 MHz外部数据总线宽度：24
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQCC-J68JESD-609代码：e0
长度：24.18 mm低功率模式：YES
湿度敏感等级：NOT SPECIFIED端子数量：68
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：COMMERCIAL
座面最大高度：4.45 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：24.18 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

ADSP-2103KP-40 数据手册

 浏览型号ADSP-2103KP-40的Datasheet PDF文件第2页浏览型号ADSP-2103KP-40的Datasheet PDF文件第3页浏览型号ADSP-2103KP-40的Datasheet PDF文件第4页浏览型号ADSP-2103KP-40的Datasheet PDF文件第6页浏览型号ADSP-2103KP-40的Datasheet PDF文件第7页浏览型号ADSP-2103KP-40的Datasheet PDF文件第8页 
ADSP-21xx  
FLAGS  
(ADSP-2111 Only)  
INSTRUCTION  
REGISTER  
PROGRAM  
MEMORY  
DATA  
MEMORY  
3
BOOT  
ADDRESS  
GENERATOR  
DATA  
ADDRESS  
GENERATOR  
#2  
DATA  
ADDRESS  
GENERATOR  
#1  
SRAM  
or ROM  
SRAM  
TIMER  
PROGRAM  
SEQUENCER  
24  
16  
PMA BUS  
DMA BUS  
14  
PMA BUS  
DMA BUS  
14  
EXTERNAL  
ADDRESS  
BUS  
MUX  
14  
24  
PMD BUS  
PMD BUS  
DMD BUS  
24  
EXTERNAL  
DATA  
BUS  
EXCHANGE  
MUX  
BUS  
16 DMD BUS  
COMPANDING  
CIRCUITRY  
INPUT REGS  
INPUT REGS  
MAC  
INPUT REGS  
11  
HOST  
PORT  
CONTROL  
SHIFTER  
ALU  
EXTERNAL  
HOST PORT  
TRANSMIT REG  
RECEIVE REG  
TRANSMIT REG  
RECEIVE REG  
OUTPUT REGS  
OUTPUT REGS  
OUTPUT REGS  
16  
BUS  
HOST  
PORT  
DATA  
16  
SERIAL  
PORT 0  
(Not on ADSP-2105)  
SERIAL  
PORT 1  
R Bus  
HOST INTERFACE PORT  
(ADSP-2111 Only)  
5
5
Figure 1. ADSP-21xx Block Diagram  
Ser ial P or ts  
One bus grant execution mode (GO Mode) allows the ADSP-  
21xx to continue running from internal memory. A second  
execution mode requires the processor to halt while buses are  
granted.  
T he ADSP-21xx processors include two synchronous serial  
ports (“SPORT s”) for serial communications and multiproces-  
sor communication. All of the ADSP-21xx processors have two  
serial ports (SPORT 0, SPORT 1) except for the ADSP-2105,  
which has only SPORT 1.  
Each ADSP-21xx processor can respond to several different  
interrupts. T here can be up to three external interrupts,  
configured as edge- or level-sensitive. Internal interrupts can be  
generated by the timer, serial ports, and, on the ADSP-2111,  
the host interface port. T here is also a master RESET signal.  
T he serial ports provide a complete synchronous serial interface  
with optional companding in hardware. A wide variety of  
framed or frameless data transmit and receive modes of opera-  
tion are available. Each SPORT can generate an internal  
programmable serial clock or accept an external serial clock.  
Booting circuitry provides for loading on-chip program memory  
automatically from byte-wide external memory. After reset,  
three wait states are automatically generated. T his allows, for  
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as  
external boot memory. Multiple programs can be selected and  
loaded from the EPROM with no additional hardware.  
Each serial port has a 5-pin interface consisting of the following  
signals:  
Signal Nam e  
Function  
SCLK  
RFS  
T FS  
DR  
Serial Clock (I/O)  
T he data receive and transmit pins on SPORT 1 (Serial Port 1)  
can be alternatively configured as a general-purpose input flag  
and output flag. You can use these pins for event signalling to  
and from an external device. T he ADSP-2111 has three  
additional flag outputs whose states are controlled through  
software.  
Receive Frame Synchronization (I/O)  
T ransmit Frame Synchronization (I/O)  
Serial Data Receive  
DT  
Serial Data T ransmit  
T he ADSP-21xx serial ports offer the following capabilities:  
A programmable interval timer can generate periodic interrupts.  
A 16-bit count register (T COUNT ) is decremented every n  
cycles, where n–1 is a scaling value stored in an 8-bit register  
(T SCALE). When the value of the count register reaches zero,  
an interrupt is generated and the count register is reloaded from  
a 16-bit period register (T PERIOD).  
Bidir ectional—Each SPORT has a separate, double-buffered  
transmit and receive function.  
Flexible Clocking—Each SPORT can use an external serial  
clock or generate its own clock internally.  
REV. B  
–5–  
12345678...64

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