ADP3422–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1
(0 ≤ TA ≤ 85؇C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB = VDAC
(ꢀ VDACOUT), VREG = VCS– = VVID = 1.25 V, VCPUSET = 0 V, ROUT = 100 k⍀, COUT = 10 pF, CSS = 47 nF, RPWRGD = 5 k⍀ to VCC, RCLAMP = 5.1 k⍀
to VCC, HYSSET, BSHIFT, DSHIFT, and FSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, SWFB = L, unless otherwise noted. Current sunk
by a pin has a positive sign, sourced by a pin has a negative sign.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY-UVLO-SHUTDOWN
Normal Supply Current
UVLO Supply Current
Shutdown Supply Current
UVLO Threshold
ICC
ICC(UVLO)
ICCSD
6
1
15
200
mA
µA
SD = L
µA
VCCH
VCCL
VCCHYS
VCC Rising Up, VSS = 0 V
VCC Falling, VSS Floating
2.95
V
V
mV
2.7
50
UVLO Hysteresis
Shutdown Threshold (CMOS Input) VSDTH
VCC/2
POWERGOOD
Core Feedback Threshold Voltage
VCOREFBH
0.9 V < VDAC < 1.675 V
V
COREFB Rising
1.12 VDAC
1.095 VDAC
0.88 VDAC
0.855 VDAC
0.95 VCC
0
1.145 VDAC
1.12 VDAC
0.905 VDAC
0.88 VDAC
VCC
V
V
V
V
V
V
µs
VCOREFB Falling
V
V
COREFB Rising
COREFB Falling
PowerGood Output Voltage
(Open Drain Output)
Blanking Time
VPWRGD
VCOREFB = VDACOUT
COREFB = 0.8 VDACOUT
tPWRGD,BLNK VCC = 3.3 V
V
0.8
2
100
SOFT-START/HICCUP TIMER
Charge/Discharge Current
ISS
VSS = 0.5 V
VSS = 0.5 V, VCC = 2.5 V
VREG = 1.25 V,
–16
0.6
µA
µA
Soft-Start Enable/Hiccup
Termination Threshold
VSSEN
V
RAMP = VCOREFB = 1.27 V
VSS Falling
SS Rising
150
200
200
mV
mV
V
Soft-Start Termination/Hiccup
Enable Threshold
VSSTERM
VRAMP = VCOREFB = 1.27 V
VSS Rising
VSS Falling
2.05
2.0
V
V
VID DAC
VID Input Threshold (CMOS Inputs) VVID0...4
0.8
10
0.7 VCC
40
V
µA
VID Input Current
IVID0...4
VID 0...4 = L
(Internal Active Pull-up)
Output Voltage
VDAC
See VID Code Table 1
0.600
–0.85
1.750
+0.85
V
%
µs
Output Voltage Accuracy
⌬VDAC/VDAC
tDACS
4
Output Voltage Settling Time3
1.3
CORE COMPARATOR
Input Offset Voltage
Input Bias Current
Output Voltage
VCOREOS
IREG
VOUT_H
VOUT_L
VREG = 1.25 V
VREG = VRAMP = 1.25 V
VCC = 3.0 V
1.5
0.3
mV
µA
V
2.5
0
3.0
0.4
VCC = 3.6 V
V
Propagation Delay Time3
Rise and Fall Time2
tRMPOUT_PD
50
ns
ns
ns
ns
ns
V
5
6
tOUT_R
tOUT_F
3
3
10
10
6
Blanking Time
tBLNK
OUT L-H Transition
OUT H-L Transition
75
140
VCC/2
Switch Feedback Threshold
(CMOS Input)
VSWFB_TH
–2–
REV. 0