Datasheet > ADP3422JRUZ-REEL

ADP3422JRUZ-REEL

更新时间： 2024-02-04 14:21:17

品牌	Logo	应用领域
安森美 - ONSEMI		光电二极管
页数	文件大小	规格书
16页	166K
描述
IC 5-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO28, TSSOP-28, Power Management Circuit

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ADP3422JRUZ-REEL 数据手册

ADP3422–SPECIFICATIONS _(continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

LOW-SIDE DRIVE CONTROL

Output Voltage (CMOS Output)

V_DRVLSD

I_DRVLSD

DPRSLP = H

DPRSLP = L

V_DRVLSD= 1.5 V

DPRSLP = L

DPRSLP = H

0.4

V_CC

0.7 V_CC

Output Current

+0.4

–0.4

OVER/REVERSE VOLTAGE

PROTECTION

Over-Voltage Threshold

V_COREFB,OVPV_COREFBRising

V_COREFBFalling

V_COREFB,RVPV_COREFBFalling

2.0

1.8

–0.3

–0.05

2.2

Reverse-Voltage Threshold

V_COREFBRising

Output Current (Open Drain Output) I_CLAMP

V_CLAMP= 1.5 V

_COREFB= 2.2 V

V_COREFB= V_DACOUT= 1.25 V

µA

NOTES

¹All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

²Two test conditions:

1. PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V_COREFB,BAD= 1.0 V at V_VID= 1.25 V setting) to the COREFB pin right

after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time.

2. PWRGD is forced to fail (V_COREFB,BAD= 1.0 V at V_VID= 1.25 V setting) but gets into the CoreGood-window (V_COREFB,GOOD= 1.25 V) right after the moment that

BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time.

³Guaranteed by characterization.

⁴Measured from 50% of VID code transition amplitude to the point where V_DACOUTsettles within 1% of its steady state value.

⁵40 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.

⁶Measured between the 30% and 70% points of the output voltage swing.

Specifications subject to change without notice.

–4–

REV. 0

1 2 345 6 7...16

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