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ADP3422JRU-REEL7 PDF预览

ADP3422JRU-REEL7

更新时间： 2024-01-12 22:44:47
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
16页 162K
描述
IC 5-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO28, TSSOP-28, Power Management Circuit

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ADP3422JRU-REEL7 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：SSOP包装说明：TSSOP-28
针数：28Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.15模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：R-PDSO-G28JESD-609代码：e0
长度：9.7 mm湿度敏感等级：1
信道数量：5功能数量：1
端子数量：28最高工作温度：85 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.1 mm
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：OTHER端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

ADP3422JRU-REEL7 数据手册

 浏览型号ADP3422JRU-REEL7的Datasheet PDF文件第1页浏览型号ADP3422JRU-REEL7的Datasheet PDF文件第2页浏览型号ADP3422JRU-REEL7的Datasheet PDF文件第3页浏览型号ADP3422JRU-REEL7的Datasheet PDF文件第5页浏览型号ADP3422JRU-REEL7的Datasheet PDF文件第6页浏览型号ADP3422JRU-REEL7的Datasheet PDF文件第7页 
ADP3422–SPECIFICATIONS (continued)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
LOW-SIDE DRIVE CONTROL  
Output Voltage (CMOS Output)  
VDRVLSD  
IDRVLSD  
DPRSLP = H  
DPRSLP = L  
VDRVLSD = 1.5 V  
DPRSLP = L  
DPRSLP = H  
0.4  
VCC  
V
V
0.7 VCC  
Output Current  
+0.4  
–0.4  
mA  
mA  
OVER/REVERSE VOLTAGE  
PROTECTION  
Over-Voltage Threshold  
VCOREFB,OVP VCOREFB Rising  
VCOREFB Falling  
VCOREFB,RVP VCOREFB Falling  
2.0  
1.8  
–0.3  
–0.05  
2.2  
10  
V
V
V
V
Reverse-Voltage Threshold  
VCOREFB Rising  
Output Current (Open Drain Output) ICLAMP  
VCLAMP = 1.5 V  
COREFB = 2.2 V  
VCOREFB = VDACOUT = 1.25 V  
V
µA  
mA  
1
4
NOTES  
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.  
2Two test conditions:  
1. PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right  
after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time.  
2. PWRGD is forced to fail (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) but gets into the CoreGood-window (VCOREFB,GOOD = 1.25 V) right after the moment that  
BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time.  
3Guaranteed by characterization.  
4Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within 1% of its steady state value.  
540 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.  
6Measured between the 30% and 70% points of the output voltage swing.  
Specifications subject to change without notice.  
–4–  
REV. 0  
1234567...16

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