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ADP3120AJRZ

更新时间： 2024-01-01 07:39:44

品牌	Logo	应用领域
安森美 - ONSEMI		驱动器接口集成电路光电二极管
页数	文件大小	规格书
8页	128K
描述
Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

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数据手册

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ADP3120AJRZ 数据手册

ADP3120A

TSD

BST

UVLO

DRVH

FALLING

EDGE

DELAY

MONITOR

SWN

FALLING

EDGE

DELAY

START

STOP

NON−OVERLAP

MIN DRVL

TIMERS

OFF TIMER

DRVL

PGND

Figure 1. Block Diagram

PIN DESCRIPTION

SO−8

DFN8

Symbol

Description

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds

this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value

is between 100 nF and 1.0 mF. An external diode is required with the ADP3120A.

Logic−Level Input. This pin has primary control of the drive outputs.

Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.

Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.

Output drive for the lower MOSFET.

DRVL

PGND

SWN

Power Ground. Should be closely connected to the source of the lower MOSFET.

Switch Node. Connect to the source of the upper MOSFET.

Output drive for the upper MOSFET.

DRVH

http://onsemi.com

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