Data Sheet
ADP1752/ADP1753
ABSOLUTE MAXIMUM RATINGS
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in × 3 in circuit
board. Refer to JEDEC JESD51-7 for detailed information about
board construction. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP) at www.analog.com.
Table 3.
Parameter
Rating
VIN to GND
VOUT to GND
−0.3 V to +4.0 V
−0.3 V to VIN
EN to GND
−0.3 V to VIN
SS to GND
−0.3 V to VIN
PG to GND
−0.3 V to +4.0 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +125°C
150°C
SENSE/ADJ to GND
Storage Temperature Range
Junction Temperature Range
Junction Temperature
Soldering Conditions
JEDEC J-STD-020
Ψ
JB is the junction-to-board thermal characterization parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
with units of °C /W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12 document,
Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than
through a single path as in thermal resistance, θJB. Therefore,
THERMAL DATA
ΨJB thermal paths include convection from the top of the package
as well as radiation from the package, factors that make ΨJB more
useful in real-world applications. Maximum junction temperature
(TJ) is calculated from the board temperature (TB) and the power
dissipation (PD) using the following formula:
Absolute maximum ratings apply individually only, not in
combination. The ADP1752/ADP1753 may be damaged if the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient tempera-
ture may need to be derated. In applications with moderate
power dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). TJ is calculated using the following formula:
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for more
detailed information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
ΨJB
Unit
16-Lead LFCSP with Exposed Pad (CP-16-4) 42
25.5 °C/W
TJ = TA + (PD × θJA).
ESD CAUTION
Rev. E | Page 5 of 20
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