Datasheet > ADP1740ACPZ-1.8-R7

ADP1740ACPZ-1.8-R7

更新时间： 2024-01-05 02:39:54

品牌	Logo	应用领域
亚德诺 - ADI		稳压器调节器输出元件
页数	文件大小	规格书
20页	743K
描述
2 A, Low VIN, Low Dropout Linear Regulator

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技术参数
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ADP1740ACPZ-1.8-R7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC16,.16SQ,25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.18
可调性：	FIXED	最大回动电压 1：	0.28 V
标称回动电压 1：	0.16 V	最大绝对输入电压：	3.6 V
最大输入电压：	3.6 V	最小输入电压：	1.6 V
JESD-30 代码：	S-XQCC-N16	JESD-609代码：	e3
长度：	4 mm	最大电网调整率：	0.00756%
最大负载调整率：	0.0179%	湿度敏感等级：	3
功能数量：	1	输出次数：	1
端子数量：	16	工作温度TJ-Max：	125 °C
工作温度TJ-Min：	-40 °C	最大输出电流 1：	2 A
最大输出电压 1：	1.836 V	最小输出电压 1：	1.764 V
标称输出电压 1：	1.8 V	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC16,.16SQ,25
封装形状：	SQUARE	封装形式：	CHIP CARRIER
包装方法：	TAPE AND REEL	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	调节器类型：	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：	1 mm	子类别：	Other Regulators
表面贴装：	YES	技术：	CMOS
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	最大电压容差：	2%
宽度：	4 mm	Base Number Matches：	1

ADP1740ACPZ-1.8-R7 数据手册

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Data Sheet

ADP1740/ADP1741

ABSOLUTE MAXIMUM RATINGS

board design is required. The value of θ_JAmay vary, depending

on PCB material, layout, and environmental conditions. The

specified values of θ_JAare based on a 4-layer, 4 in × 3 in circuit

board. Refer to JEDEC JESD51-7 for detailed information about

board construction. For more information, see the AN-772

Application Note, A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP), at www.analog.com.

Table 3.

Parameter

Rating

VIN to GND

VOUT to GND

−0.3 V to +4.0 V

−0.3 V to V_IN

EN to GND

−0.3 V to V_IN

SS to GND

−0.3 V to V_IN

PG to GND

−0.3 V to +4.0 V

−0.3 V to V_IN

−65°C to +150°C

−40°C to +125°C

150°C

Ψ_JBis the junction-to-board thermal characterization parameter

SENSE/ADJ to GND

Storage Temperature Range

Junction Temperature Range

Junction Temperature

Soldering Conditions

with units of °C/W. Ψ_JBof the package is based on modeling and

calculation using a 4-layer board. The JEDEC JESD51-12

document, Guidelines for Reporting and Using Electronic Package

Thermal Information, states that thermal characterization

parameters are not the same as thermal resistances. Ψ_JBmeasures

the component power flowing through multiple thermal paths

rather than through a single path, as in thermal resistance (θ_JB).

Therefore, Ψ_JBthermal paths include convection from the top of

the package, as well as radiation from the package, factors that

make Ψ_JBmore useful in real-world applications. Maximum

junction temperature (T_J) is calculated from the board temper-

ature (T_B) and the power dissipation (P_D) using the following

formula:

JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL DATA

Absolute maximum ratings apply only individually, not in

combination. The ADP1740/ADP1741 may be damaged when

junction temperature limits are exceeded. Monitoring ambient

temperature does not guarantee that the junction temperature is

within the specified temperature limits. In applications with

high power dissipation and poor PCB thermal resistance, the

maximum ambient temperature may need to be derated. In

applications with moderate power dissipation and low PCB

thermal resistance, the maximum ambient temperature can

exceed the maximum limit as long as the junction temperature

is within specification limits.

T_J= T_B+ (P_D× Ψ_JB)

Refer to the JEDEC JESD51-8 and JESD51-12 documents for

more detailed information about Ψ_JB.

THERMAL RESISTANCE

θ_JAand Ψ_JBare specified for the worst-case conditions, that is, a

device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type

16-Lead LFCSP with Exposed Pad

θ_JA

Ψ_JB

Unit

25.5

°C/W

The junction temperature (T_J) of the device is dependent on the

ambient temperature (T_A), the power dissipation of the device

(P_D), and the junction-to-ambient thermal resistance of the

package (θ_JA). T_Jis calculated using the following formula:

ESD CAUTION

T_J= T_A+ (P_D× θ_JA)

The junction-to-ambient thermal resistance (θ_JA) of the package

is based on modeling and calculation using a 4-layer board. The

junction-to-ambient thermal resistance is highly dependent on

the application and board layout. In applications where high

maximum power dissipation exists, close attention to thermal

Rev. E | Page 5 of 20

1 2 3 456 7 8...20

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