Datasheet > ADP1740

ADP1740

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		稳压器
页数	文件大小	规格书
6页	165K
描述
2 A, Low Dropout, CMOS Linear Regulator

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ADP1740 数据手册

ADP1740/ADP1741

Preliminary Technical Data

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

12 OUT

11 OUT

10 OUT

12 OUT

11 OUT

10 OUT

ADP1740

TOP VIEW

(Not to Scale)

ADP1741

TOP VIEW

(Not to Scale)

SENSE

9 ADJ

NC = NO CONNECT

Figure 3. ADP1740 Pin Configuration

Figure 4. ADP1741 Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

ADP1741

Mnemonic Description

ADP1740

1, 2, 3, 15, 16

Regulator Input Supply. Bypass IN to GND with a 4.7 μF or greater capacitor. Note

that all five pins must be connected to source

Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the

regulator. For automatic startup, connect EN to IN.

Power Good. This open-drain output requires an external pull-up resistor to IN. If

part is in shutdown, current limit, thermal shutdown, or falls below 90% of the

nominal output voltage, PG immediately transitions low.

N/A

GND

Ground.

Soft Start. A capacitor connected to this pin determines the soft start time.

Not connected. No internal connection

Sense. Measures the actual output voltage at the load and feeds it to the error

amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR

drop between the regulator output and the load.

SENSE

N/A

ADJ

Adjust. A resistor divider from OUT to ADJ sets the output voltage.

10, 11, 12, 13, 14

OUT

Regulated Output Voltage. Bypass OUT to GND with a 4.7 μF or greater capacitor.

Note that all five pins must be connected to load

Exposed pad on the bottom of the LFCSP package. EP enhances thermal

performance and is electrically connected to GND inside the package. It is

recommended to connect EP to the ground plane on the board.

registered trademarks are the property of their respective owners.

PR07081-0-11/07(PrA)

Rev. PrA | Page 6 of 6

1...3 4 56

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