Datasheet > ADP1740

ADP1740

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚德诺 - ADI		稳压器
页数	文件大小	规格书
6页	165K
描述
2 A, Low Dropout, CMOS Linear Regulator

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ADP1740 数据手册

Preliminary Technical Data

SPECIFICATIONS

ADP1740/ADP1741

V_IN= (V_OUT+ 0.4 V) or 1.8 V (whichever is greater), I_OUT= 10 mA, C_IN= C_OUT= 4.7 μF, T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Test Conditions

Min

Typ

Max

Unit

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

T_J= −40°C to +125°C

I_OUT= 0 mA

I_OUT= 100 mA

I_OUT= 100 mA, T_J= −40°C to +125°C

I_OUT= 2 A

I_OUT= 2 A, T_J= −40°C to +125°C

EN = GND

1.6

3.6

I_GND

500

μA

TBD

1.3

TBD

SHUTDOWN CURRENT

I_GND-SD

EN = GND, T_J= −40°C to +125°C

OUTPUT VOLTAGE ACCURACY

Fixed Output Voltage Accuracy

(ADP1740)

V_OUT

I_OUT= 10 mA

I_OUT= 1 mA to 2 A

1 mA < I_OUT< 2 A, T_J= −40°C to +125°C

I_OUT= 10 mA

I_OUT= 1 mA to 2 A

−1

−1.5

−2.5

+1.5

+2.5

Adjustable Output Voltage Accuracy

(ADP1741)¹

V_OUT

0.743 0.75 0.758

0.739

0.731

−0.1

0.761

0.769

+0.1

1 mA < I_OUT< 2 A, T_J= −40°C to +125°C

LINE REGULATION

∆V_OUT/∆V_IN

V_IN= (V_OUT+ 0.4 V) to 3.6 V,

T_J= −40°C to +125°C

%/V

LOAD REGULATION²

DROPOUT VOLTAGE³

∆V_OUT/∆I_OUT

V_DROPOUT

I_OUT= 10 mA to 2 A, T_J= −40°C to +125°C

I_OUT= 100 mA, V_OUT≥ 1.8 V

I_OUT= 100 mA, V_OUT≥ 1.8 V,

T_J= −40°C to +125°C

TBD

%/mA

I_OUT= 2 A, V_OUT≥ 1.8 V

I_OUT= 2 A, V_OUT≥ 1.8 V, T_J= −40°C to +125°C

200

350

START-UP TIME⁴

t_START-UP

I_LIMIT

ADP1740 and ADP1741

CURRENT LIMIT THRESHOLD⁵

THERMAL SHUTDOWN

C_SS= 10 nF, I_OUT= 10 mA

T_Jrising

4.8

TBD

1.0

TBD

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

TS_SD

150

°C

TS_SD-HYS

PG OUTPUT LOGIC LEVEL

PG Output Logic High

PG Output Logic Low

PG Output Delay from EN Transition

Low to High

PG_HIGH

PG_LOW

1.6 V ≤ V_IN≤ 3.6 V, I_OH< 1 μA

1.6 V ≤ V_IN≤ 3.6 V, I_OL<2 mA

1.6 V ≤ V_IN≤ 3.6 V, C_SS= 10 nF

0.4

TBD

PG OUTPUT THRESHOLD

PG Threshold, Output Voltage Falling

PG Threshold, Output Voltage Rising

EN INPUT

PG_FALL

PG_RISE

1.6 V ≤ V_IN≤ 3.6 V

−10

−7

EN Input Logic High

EN Input Logic Low

EN Input Leakage Current

SOFT START INPUT

V_IH

V_IL

V_I-LEAKAGE

1.6 V ≤ V_IN≤ 3.6 V

EN = IN or GND

1.0

μA

0.4

0.1

Soft Start Current

I_SS

1.6 V ≤ V_IN≤ 3.6 V

TBD

100

μA

ADJ INPUT BIAS CURRENT (ADP1741)

SENSE INPUT BIAS CURRENT

OUTPUT NOISE

ADJ_I-BIAS

SNS_I-BIAS

OUT_NOISE

1.6 V ≤ V_IN≤ 3.6 V

μA

10 Hz to 100 kHz, V_OUT= 0.75 V

10 Hz to 100 kHz, V_OUT= 2.5V

μV rms

Rev. PrA | Page 3 of 6

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