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ADP1712AUJZ-0.85R7 PDF预览

ADP1712AUJZ-0.85R7

更新时间： 2024-02-03 17:20:09
品牌 Logo 应用领域
亚德诺 - ADI 线性稳压器IC调节器电源电路光电二极管输出元件
页数 文件大小 规格书
16页 491K
描述
300 mA, Low Dropout CMOS Linear Regulator

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ADP1712AUJZ-0.85R7 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSOT
包装说明：VSSOP,针数：5
Reach Compliance Code：unknown风险等级：5.67
Is Samacsys：N最大回动电压 1：0.27 V
最大输入电压：5.5 V最小输入电压：2.5 V
JESD-30 代码：R-PDSO-G5JESD-609代码：e3
长度：2.9 mm湿度敏感等级：1
功能数量：1端子数量：5
工作温度TJ-Max：125 °C工作温度TJ-Min：-40 °C
最大输出电流 1：0.3 A最大输出电压 1：0.867 V
最小输出电压 1：0.833 V标称输出电压 1：0.85 V
封装主体材料：PLASTIC/EPOXY封装代码：VSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260调节器类型：FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：1 mm表面贴装：YES
技术：CMOS端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1.6 mmBase Number Matches：1

ADP1712AUJZ-0.85R7 数据手册

 浏览型号ADP1712AUJZ-0.85R7的Datasheet PDF文件第7页浏览型号ADP1712AUJZ-0.85R7的Datasheet PDF文件第8页浏览型号ADP1712AUJZ-0.85R7的Datasheet PDF文件第9页浏览型号ADP1712AUJZ-0.85R7的Datasheet PDF文件第11页浏览型号ADP1712AUJZ-0.85R7的Datasheet PDF文件第12页浏览型号ADP1712AUJZ-0.85R7的Datasheet PDF文件第13页 
ADP1712/ADP1713/ADP1714  
THEORY OF OPERATION  
SOFT-START FUNCTION (ADP1712)  
The ADP1712/ADP1713/ADP1714 are low dropout linear regula-  
tors that use an advanced, proprietary architecture to provide high  
power supply rejection ratio (PSRR) and excellent line and load  
transient response with just a small 2.2 μF ceramic output capac-  
itor. All devices operate from a 2.5 V to 5.5 V input rail and provide  
up to 300 mA of output current. Incorporating a novel scaling  
architecture, ground current is very low when driving light loads.  
Ground current in the shutdown mode is typically less than 1 μA.  
For applications that require a controlled startup, the ADP1712  
provides a programmable soft-start function. Programmable soft  
start is useful for reducing inrush current upon startup and for pro-  
viding voltage sequencing. To implement soft start, connect a small  
ceramic capacitor from SS to GND. Upon startup, a 1.2 μA current  
source charges this capacitor. The ADP1712 start-up output voltage  
is limited by the voltage at SS, providing a smooth ramp up to the  
nominal output voltage. The soft-start time is calculated by  
T
SS = VREF ×(CSS/ISS)  
where:  
SS is the soft-start period.  
REF is the 0.8 V reference voltage.  
SS is the soft-start capacitance from SS to GND.  
SS is the current sourced from SS (1.2 μA).  
(1)  
IN  
OUT  
T
V
C
I
CURRENT  
LIMIT  
THERMAL  
PROTECT  
When the ADP1712 is disabled (using EN), the soft-start capacitor  
is discharged to GND through an internal 100 Ω resistor.  
SHUTDOWN  
AND UVLO  
SS/  
ADJ/  
BYP/  
TRK  
EN  
REFERENCE  
GND  
EN  
Figure 25. Internal Block Diagram  
Internally, the ADP1712/ADP1713/ADP1714 each consist of a  
reference, an error amplifier, a feedback voltage divider, and a  
PMOS pass transistor. Output current is delivered via the PMOS  
pass device, which is controlled by the error amplifier. The error  
amplifier compares the reference voltage with the feedback volt-  
age from the output and amplifies the difference. If the feedback  
voltage is lower than the reference voltage, the gate of the PMOS  
device is pulled lower, which allows more current to pass and  
increases the output voltage. If the feedback voltage is higher than  
the reference voltage, the gate of the PMOS device is pulled higher,  
allowing less current to pass and decreasing the output voltage.  
1
OUT  
V
V
C
= 5V  
= 3.3V  
IN  
OUT  
= 2.2μF  
OUT  
2
C
= 22nF  
SS  
I
= 300mA  
LOAD  
TIME (4ms/DIV)  
Figure 26. OUT Ramp-Up with External Soft-Start Capacitor  
The ADP1712 adjustable version, ADP1713, and ADP1714 have  
no pins for soft start, so the function is switched to an internal  
soft-start capacitor. This sets the soft-start ramp-up period to  
approximately 24 μs.  
The ADP1712 is available in two versions, one with a fixed output  
voltage and one with an adjustable output voltage. The fixed output  
voltage is set internally to one of sixteen values between 0.75 V and  
3.3 V, using an internal feedback network. The adjustable output  
voltage can be set to between 0.8 V and 5.0 V by an external voltage  
divider connected from OUT to ADJ. The ADP1713 and ADP1714  
are available in fixed output voltage options only. The ADP1712  
fixed version allows an external soft-start capacitor to be connected  
between the SS pin and GND, which controls the output voltage  
ramp during startup. The ADP1713 allows a reference bypass  
capacitor to be connected between the BYP pin and GND, which  
reduces output voltage noise and improves power supply rejection.  
The ADP1714 features a track pin, which allows the output voltage  
to follow the voltage at the TRK pin.  
EN  
1
V
V
C
= 5V  
IN  
OUT  
OUT  
= 1.6V  
= 2.2μF  
= 10mA  
2
OUT  
I
LOAD  
A logic on the EN pin determines if the output is active. When EN  
is high, the output is on, and when EN is low, the output is off.  
TIME (20µs/DIV)  
Figure 27. OUT Ramp-Up with Internal Soft-Start  
Rev. A | Page 10 of 16  
 
 
 
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