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ADP1707ACPZ-075R7 PDF预览

ADP1707ACPZ-075R7

更新时间: 2022-07-15 11:27:41
品牌 Logo 应用领域
亚德诺 - ADI 稳压器
页数 文件大小 规格书
20页 563K
描述
1 A, Low Dropout, CMOS Linear Regulator

ADP1707ACPZ-075R7 数据手册

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ADP1706/ADP1707/ADP1708  
THEORY OF OPERATION  
providing a smooth ramp-up to the nominal output voltage.  
The soft start time is calculated by  
The ADP1706/ADP1707/ADP1708 are low dropout linear  
regulators that use an advanced, proprietary architecture to  
provide high power supply rejection ratio (PSRR) and excellent  
line and load transient response with a small 4.7 μF ceramic  
output capacitor. All devices operate from a 2.5 V to 5.5 V input  
rail and provide up to 1 A of output current. Supply current in  
shutdown mode is typically 100 nA.  
T
SS = VREF ×(CSS/ISS)  
where:  
SS is the soft start period.  
REF is the 0.8 V reference voltage.  
SS is the soft start capacitance from SS to GND.  
SS is the current sourced from SS (1.2 μA).  
(1)  
T
V
C
I
When the ADP1706 is disabled (using EN), the soft start capacitor  
is discharged to GND through an internal 100 Ω resistor.  
IN  
OUT  
SENSE  
CURRENT LIMIT  
THERMAL PROTECT  
EN  
SHUTDOWN  
ADJ/  
TRK/  
SS  
2
EN  
SOFT  
START  
REFERENCE  
OUT  
GND  
V
V
= 5V  
= 3.3V  
IN  
OUT  
Figure 27. Internal Block Diagram  
C
C
I
= 4.7μF  
OUT  
1
= 10nF  
= 1A  
SS  
Internally, the ADP1706/ADP1707/ADP1708 consist of a  
LOAD  
reference, an error amplifier, a feedback voltage divider, and a  
PMOS pass transistor. Output current is delivered via the  
PMOS pass device, which is controlled by the error amplifier.  
The error amplifier compares the reference voltage with the  
feedback voltage from the output and amplifies the difference. If  
the feedback voltage is lower than the reference voltage, the gate  
of the PMOS device is pulled lower, allowing more current  
to pass and increasing the output voltage. If the feedback  
voltage is higher than the reference voltage, the gate of the  
PMOS device is pulled higher, allowing less current to pass  
and decreasing the output voltage.  
TIME (2ms/DIV)  
Figure 28. OUT Ramp-Up with External Soft Start Capacitor  
The ADP1707 and ADP1708 have no pins for soft start;  
therefore, the function is switched to an internal soft start  
capacitor, which sets the soft start ramp-up period to approxi-  
mately 48 μs. Note that the ramp-up period is the time it takes  
OUT to go from 0% to 90% of the nominal value and is  
different from the start-up time in Table 1, which is the time  
between the rising edge of EN to OUT being at 90% of the  
nominal value. For the worst-case output voltage of 5 V, using  
the suggested 4.7 μF output capacitor, the resulting input  
inrush current is approximately 490 mA, which is less than  
the maximum 1 A load current.  
The ADP1706/ADP1707 are available in 16 fixed output voltage  
options between 0.75 V and 3.3 V. The ADP1706 allows for  
connection of an external soft start capacitor, which controls  
the output voltage ramp during startup. The ADP1707 features  
a TRK pin that allows the output voltage to follow the voltage at  
this pin. The ADP1708 is available in an adjustable version with  
an output voltage that can be set to between 0.8 V and 5.0 V by  
an external voltage divider. All devices are controlled by an  
enable pin (EN).  
EN  
2
SOFT START FUNCTION (ADP1706)  
For applications that require a controlled startup, the ADP1706  
provides a programmable soft start function. The programma-  
ble soft start is useful for reducing inrush current upon startup  
and for providing voltage sequencing. To implement a soft start,  
connect a small ceramic capacitor from SS to GND. Upon  
startup, a 1.2 μA current source charges this capacitor. The  
ADP1706 start-up output voltage is limited by the voltage at SS,  
V
V
= 5V  
= 1.6V  
IN  
OUT  
OUT  
1
C
I
= 4.7μF  
= 10mA  
OUT  
LOAD  
TIME (20µs/DIV)  
Figure 29. OUT Ramp-Up with Internal Soft Start  
Rev. 0 | Page 10 of 20  
 
 
 

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