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ADP122AUJZ-2.8-R7 PDF预览

ADP122AUJZ-2.8-R7

更新时间: 2024-01-18 23:32:31
品牌 Logo 应用领域
亚德诺 - ADI 稳压器
页数 文件大小 规格书
20页 617K
描述
5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator

ADP122AUJZ-2.8-R7 数据手册

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ADP122/ADP123  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
5
1
2
3
VIN  
GND  
EN  
VOUT  
1
2
3
5
4
VIN  
GND  
EN  
VOUT  
ADJ  
ADP122  
ADP123  
TOP VIEW  
TOP VIEW  
(Not to Scale)  
(Not to Scale)  
4
NC  
NC = NO CONNECT  
Figure 3. ADP122 Fixed Output Pin Configuration  
Figure 4. ADP123 Adjustable Output Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No.  
ADP122 ADP123 Mnemonic Description  
1
2
3
1
2
3
VIN  
GND  
EN  
Regulator Input Supply. Bypass VIN to GND with a capacitor of at least 1 μF.  
Ground.  
Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For  
automatic startup, connect EN to VIN.  
N/A  
4
ADJ  
Output Voltage Adjust Input. Connect the midpoint of an external divider from VOUT to GND to this  
pin to set the output voltage.  
4
5
N/A  
5
NC  
VOUT  
Not Connected Internally.  
Regulated Output Voltage. Bypass VOUT to GND with a capacitor of at least 1 μF.  
Rev. 0 | Page 6 of 20  
 

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