ADN2850
Parameter
Symbol
Conditions
Min
Typ2
Max
Unit
INTERFACE TIMING CHARACTERISTICS (apply to all parts)5, 11
Clock Cycle Time (tCYC
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulsewidth
Data Setup Time
)
t1
t2
t3
t4 , t5
t6
20
10
1
10
5
ns
ns
tCYC
ns
ns
Clock Level High or Low
From Positive CLK Transition
From Positive CLK Transition
Data Hold Time
t7
5
ns
CS to SDO – SPI Line Acquire
CS to SDO – SPI Line Release
CLK to SDO Propagation Delay12
CS High Pulsewidth13
t8
t9
40
50
50
ns
ns
ns
ns
tCYC
ns
ms
ms
ns
ns
µs
t10
t12
t13
t14
t15
RP = 2.2 kΩ, CL < 20 pF
10
4
0
CS High to CS High13
RDY Rise to CS Fall
CS Rise to RDY Fall Time
0.15
35
0.3
Read/Store to Nonvolatile EEMEM14 t16
Applies to Command 2H, 3H, 9H
CS Rise to Clock Edge Setup
Preset Pulsewidth (Asynchronous)
Preset Response Time to Wiper Setting tPRESP
t17
tPRW
10
50
Not Shown in Timing Diagram
PR Pulsed Low to Refresh
Wiper Positions
140
100
FLASH/EE MEMORY RELIABILITY
Endurance15
100
K Cycles
Years
Data Retention16
NOTES
1 Parts can be operated at 2.7 V single supply, except from 08C to –408C, where minimum 3 V is needed.
2 Typicals represent average readings at 258C and VDD = 5 V.
3 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA for VDD = 2.7 V and IW ~ 400 µA for VDD = 5 V.
4 Resistor terminals W and B have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V DD/2.
7 Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.
8 PDISS is calculated from (IDD ꢀ VDD) + (ISS ꢀ VSS).
9 Applies to photodiode of optical receiver.
10 All dynamic characteristics use VDD = +2.5 V and VSS = –2.5 V.
11 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using both VDD = 3 V and 5 V.
12 Propagation delay depends on value of VDD, RPULL_UP, and CL. See Applications section.
13 Valid for commands that do not activate the RDY pin.
14 RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation at TA = –40°C
and VDD < 3 V extends the save time to 35 ms.
15 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
16 Retention lifetime equivalent at junction temperature (TJ ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V will
derate with junction temperature.
Specifications subject to change without notice.
The ADN2850 contains 16,000 transistors. Die size: 93 mil ꢀ 103 mil, 10,197 sq mil.
REV. B
–3–
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