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ADN2855ACPZ-R7 PDF预览

ADN2855ACPZ-R7

更新时间: 2024-01-06 06:47:44
品牌 Logo 应用领域
亚德诺 - ADI 外围集成电路
页数 文件大小 规格书
21页 433K
描述
Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with Deserializerer

ADN2855ACPZ-R7 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantECCN代码:5A991.B.3
HTS代码:8542.39.00.01风险等级:5.07
Is Samacsys:NJESD-30 代码:S-XQCC-N32
JESD-609代码:e3长度:5 mm
湿度敏感等级:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:5 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

ADN2855ACPZ-R7 数据手册

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Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps  
Burst Mode Clock and Data Recovery IC with Deserializer  
Data Sheet  
ADN2855  
FEATURES  
GENERAL DESCRIPTION  
Serial data input  
The ADN2855 is a burst mode clock and data recovery IC  
155.52 Mbps/622.08 Mbps/1244.16 Mbps/1250.00 Mbps  
12-bit acquisition time  
4-bit parallel LVDS output interface  
Patented dual-loop clock recovery architecture  
Integrated PRBS generator  
Byte rate reference clock  
Loss-of-lock indicator  
Supports double data rate (DDR)-compatible FPGA  
I2C interface to access optional features  
Single-supply operation: 3.3 V  
designed for GPON/BPON/GEPON optical line terminal (OLT)  
receiver applications. The part can operate at 155.52 Mbps,  
622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable  
via the I2C interface.  
The ADN2855 frequency locks to the OLT reference clock and  
aligns to the input data within 12 bits of the start of the preamble.  
The device provides a full rate or an optional half rate output  
clock for a double data rate (DDR) interface to an FPGA or  
digital ASIC.  
All specifications are quoted for −40°C to +85°C ambient tempera-  
ture, unless otherwise noted. The ADN2855 is available in a  
compact 5 mm × 5 mm, 32-lead chip scale package.  
Power  
670 mW typical in serial output mode  
825 mW typical in deserializer mode  
5 mm × 5 mm, 32-lead LFCSP  
APPLICATIONS  
Passive optical networks  
GPON/BPON/GEPON OLT receivers  
FUNCTIONAL BLOCK DIAGRAM  
REFCLKP,  
REFCLKN  
DATAV  
CF1  
CF2 VCC  
VEE  
ADN2855  
LOOP  
FILTER  
FREQUENCY/  
LOCK  
DETECT  
RESET  
PIN  
NIN  
PHASE  
SHIFTER  
PHASE  
DETECT  
LOOP  
FILTER  
CML INPUT  
BUFFER  
VCO  
DATA  
RE-TIMING  
2
SDA  
SCK  
2
I C  
DIVIDER  
DESERIALIZER  
SQUELCH  
4 × 2  
2
DATxP,  
DATxN  
CLKOUTP,  
CLKOUTN  
Figure 1.  
Rev. B  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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