ADM8696/ADM8697
CIRCUIT INFO RMATIO N
Batter y Switchover Section (AD M8696)
Low Line RESET O UTP UT
RESET is an active low output that provides a RESET signal to
the microprocessor whenever the Low Line Input (LLIN) is be-
low 1.3 V. T he LLIN input is normally used to monitor the
power supply voltage. An internal timer holds RESET low for
50 ms after the voltage on LLIN rises above 1.3 V. T his is in-
tended as a power-on RESET signal for the processor. It allows
time for the power supply and microprocessor to stabilize. On
power-down, the RESET output remains low, with VCC as low
as 1 V. T his ensures that the microprocessor is held in a stable
shutdown condition.
The battery switchover circuit is designed to switch over to
battery backup in the event of a power failure. When LLIN
is below the reset threshold and VCC is below VBAT T , then
VBAT T is switched to VOUT
.
During normal operation, with VCC higher than VBAT T, VCC is
internally switched to VOUT via an internal PMOS transistor
switch. T his switch has a typical on resistance of 0.7 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instanta-
neous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to VOUT . T he capacitor
will provide the peak current transients to the RAM. A capaci-
tance value of 0.1 µF or greater may be used.
T he LLIN comparator has approximately 12 mV of hysteresis
for enhanced noise immunity.
In addition to RESET, an active high RESET output is also
available. T his is the complement of RESET and is useful for
processors requiring an active high RESET .
If the continuous output current requirement at VOUT exceeds
100 mA or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. T he BAT T ON output can directly
drive the base of the external transistor.
V2
V2
LLIN
V1
V1
A 7 Ω MOSFET switch connects the VBAT T input to VOUT dur-
ing battery backup. T his MOSFET has very low input-to-out-
put differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. T he supply current in battery backup is typi-
cally 0.4 µA.
t1
t
1
RESET
LOW LINE
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
T he ADM8696 operates with battery voltages from 2.0 V to
VCC–0.3 V). High value capacitors, either standard electrolytic
or the farad-size double layer capacitors, can also be used for
short-term memory backup. A small charging current of typi-
cally 10 nA (0.1 µA max) flows out of the VBAT T terminal. T his
current is useful for maintaining rechargeable batteries in a fully
charged condition. T his extends the life of the backup battery
by compensating for its self-discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1 µA) is safe
for even the smallest lithium cells.
Figure 2. Power-Fail Reset Tim ing
Watchdog Tim er RESET
T he watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a RESET pulse is generated. T he
ADM8696/ADM8697 may be configured for either a fixed
“short” 100 ms or a “long” 1.6 second timeout period or for an
adjustable timeout period. If the “short” period is selected,
some systems may be unable to service the watchdog timer im-
mediately after a reset, so a “long” timeout is automatically ini-
tiated directly after a reset is issued. T he watchdog timer is
restarted at the end of Reset, whether the Reset was caused by
lack of activity on WDI or by LLIN falling below the reset
threshold.
If the battery switchover section is not used, VBAT T should be
connected to GND and VOUT should be connected to VCC
.
V
CC
V
OUT
V
BATT
GATE DRIVE
100
T he normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. T he
watchdog timeout period restarts with each transition on the
WDI pin. T o ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 s). T he watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
mV
BATT ON
(ADM8691, ADM8693,
ADM8695, ADM8696)
700
mV
INTERNAL
SHUTDOWN SIGNAL
WHEN
V
> (V + 0.7V)
BATT
CC
Figure 1. Battery Switchover Schem atic
REV. A
–5–
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