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ADM8969ARW-REEL

更新时间： 2024-02-21 16:30:01
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
13页 284K
描述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16, MS-013AA, SOIC-16

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中文翻译

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ADM8969ARW-REEL 技术参数

是否Rohs认证： 不符合生命周期：Active
零件包装代码：SOIC包装说明：MS-013AA, SOIC-16
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G16
长度：10.3 mm湿度敏感等级：1
信道数量：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：225电源：3.3/5 V
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Power Management Circuits最大供电电流 (Isup)：0.2 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

ADM8969ARW-REEL 数据手册

 浏览型号ADM8969ARW-REEL的Datasheet PDF文件第7页浏览型号ADM8969ARW-REEL的Datasheet PDF文件第8页浏览型号ADM8969ARW-REEL的Datasheet PDF文件第9页浏览型号ADM8969ARW-REEL的Datasheet PDF文件第11页浏览型号ADM8969ARW-REEL的Datasheet PDF文件第12页浏览型号ADM8969ARW-REEL的Datasheet PDF文件第13页 
ADM8696/ADM8697  
TYP ICAL AP P LICATIO NS  
AD M8696  
Figure 18b shows a similar application for the ADM8696 but in  
this case the PFI input monitors the unregulated input to the  
7805 voltage regulator. T his gives an earlier warning of an im-  
pending power failure. It is useful with processors operating at  
low speeds or where there are a significant number of house-  
keeping tasks to be completed before the power is lost.  
Figure 18 shows the ADM8696 in a typical power monitoring,  
battery backup application. VOUT powers the CMOS RAM.  
Under normal operating conditions with VCC present, VOUT is  
internally connected to VCC. If a power failure occurs, VCC will  
decay and VOUT will be switched to VBAT T, thereby maintaining  
power for the CMOS RAM.  
INPUT  
POWER  
7805  
P ower Fail RESET  
T he VCC power supply is also monitored by the Low Line In-  
put, LLIN. A RESET pulse is generated when LLIN falls below  
1.3 V. RESET will remain low for 50 ms after LLIN returns  
above 1.3 V. T his allows for a power-on reset and prevents re-  
peated toggling of RESET if the VCC power supply is unstable.  
Resistors R3 and R4 should be chosen to give the desired VCC  
reset threshold.  
0.1µF  
0.1µF  
V
BATT  
ON  
V
OUT  
CC  
3V  
BATTERY  
V
CC  
V
BATT  
CMOS RAM  
R1  
R2  
ADM8696  
PFI  
µP  
POWER  
A0–A15  
I/O LINE  
NMI  
GND  
WDI  
Watchdog Tim er  
R3  
R4  
OSC IN  
PFO  
µP  
T he Watchdog T imer Input (WDI) monitors an I/O line from  
the µP system. T his line must be toggled once every 1.6 s to  
verify correct software execution. Failure to toggle the line indi-  
cates that the µP system is not correctly executing its program  
and may be tied up in an endless loop. If this happens, a reset  
pulse is generated to initialize the processor.  
NC  
OSC SEL  
RESET  
RESET  
LL  
IN  
RESET  
LOW LINE WDO  
SYSTEM STATUS  
INDICATORS  
If the watchdog timer is not needed the WDI input should be  
left floating.  
Figure 18b. ADM8696 Typical Application Circuit B  
P ower Fail D etector  
T his application also shows an optional external transistor that  
T he Power Fail Input, PFI, monitors the input power supply via  
a resistive divider network R1 and R2. T his input is intended as  
an early warning power fail input. T he voltage on the PFI input  
is compared with a precision 1.3 V internal reference. If the in-  
put voltage drops below 1.3 V, a power fail output (PFO) signal  
is generated. T his warns of an impending power failure and may  
be used to interrupt the processor so that the system may be  
shut down in an orderly fashion. T he resistors in the sensing  
network are ratioed to give the desired power fail threshold volt-  
age VT . T he threshold should be set at a higher voltage than the  
RESET threshold so there is sufficient time available to com-  
plete the shutdown procedure before the processor is RESET  
and power is lost.  
may be used to provide in excess of 100 mA current on VOUT  
When VCC is higher than VBAT T, the BAT T ON output goes  
low, providing 25 mA of base drive for the external PNP transis-  
tor. T he maximum current available is dependent on the power  
rating of the external transistor.  
.
RAM Wr ite P r otection  
T he ADM8697 CEOUT line drives the Chip Select inputs of the  
CMOS RAM. CEOUT follows CEIN as long as LLIN is above the  
reset threshold. If LLIN falls below the reset threshold, CEOUT  
goes high, independent of the logic level at CEIN. T his prevents  
the microprocessor from writing erroneous data into RAM dur-  
ing power-up, power-down, brownouts and momentary power  
interruptions.  
+5V  
R1  
R3  
µP POWER  
V
CC  
CMOS RAM  
POWER  
V
PFI  
LL  
OUT  
IN  
RESET  
µP SYSTEM  
R2  
R4  
ADM8696  
RESET  
µP RESET  
µP NMI  
PFO  
WDI  
V
BATT  
+
I/O LINE  
BATTERY  
GND  
Figure 18a. ADM8696 Typical Application Circuit A  
REV. A  
–10–  
1...78910111213

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