ADM705AN

更新时间： 2024-02-09 12:03:40

品牌	Logo	应用领域
亚德诺 - ADI		电源电路电源管理电路光电二极管监控输入元件
页数	文件大小	规格书
8页	144K
描述
Low Cost uP Supervisory Circuits

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技术参数
数据手册

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ADM705AN 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	0.67
其他特性：	RESET THRESHOLD VOLTAGE IS 4.65V; MANUAL RESET INPUT	可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	信道数量：	2
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	1.75 mm	子类别：	Power Management Circuits
最大供电电流 (Isup)：	0.25 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.9 mm
Base Number Matches：	1

ADM705AN 数据手册

ADM705–ADM708

If, in the event of inactivity on the WDI line, a system reset is

required, then the WDO output should be connected to the MR

input as shown in Figure 16.

= 25؇C

RESET

ADM705/

ADM706

␮P

I/O LINE

WDI

RESET

WDO

GND

Figure 16. RESET from WDO

Monitoring Additional Supply Levels

2␮s/DIV

It is possible to use the power-fail comparator to monitor a

second supply as shown in Figure 17. The two sensing resistors,

R1 and R2, are selected so that the voltage on PFI drops below

1.25 V at the minimum acceptable input supply. The PFO

output may be connected to the MR input so that a RESET is

generated when the supply drops out of tolerance. In this case, if

either supply drops out of tolerance, a RESET will be generated.

Figure 14. ADM705/ADM707 RESET Response Time

APPLICATIONS

A Typical Operating Circuit is shown in Figure 15. The unregu-

lated dc input supply is monitored using the PFI input via the

resistive divider network. Resistors R1 and R2 should be selected

so that when the supply voltage drops below the desired level

(e.g., 8 V), the voltage on PFI drops below the 1.25 V threshold

thereby generating an interrupt to the µP. Monitoring the pre-

regulator input gives additional time to execute an orderly

shutdown procedure before power is lost.

RESET

ADM705/

ADM706

␮P

PFI

PFO

ADM666

GND

OUT

UNREGULATED

Figure 17. Monitoring 5 V and an Additional Supply, V_X

RESET

WDI

␮Ps With Bidirectional RESET

I/O LINE

In order to prevent contention for microprocessors with a bidi-

rectional reset line, a current limiting resistor should be inserted

between the ADM70x RESET output pin and the µP reset pin.

This will limit the current to a safe level if there are conflicting

output reset levels. A suitable resistor value is 4.7 kΩ. If the

reset output is required for other uses, it should be buffered as

shown in Figure 18.

ADM705/

ADM706

␮P

PFI

WDO

NMI

INTERRUPT

PFO

GND

MANUAL

RESET

Figure 15. Typical Application Circuit

BUFFERED

RESET

Microprocessor activity is monitored using the WDI input. This

is driven using an output line from the processor. The software

routines should toggle this line at least once every 1.6 seconds.

If a problem occurs and this line is not toggled, WDO goes low

and a nonmaskable interrupt is generated. This interrupt rou-

tine may be used to clear the problem.

␮P

RESET

ADM70x

RESET

GND

Figure 18. Bidirectional I-O RESET

REV. B

–7–

1...4 5 678

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ADM705ARZ	ADI	Low Cost Microprocessor Supervisory Circuits	获取价格
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ADM706_15	ADI	Low Cost Microprocessor Supervisory Circuits	获取价格
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