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ADM705AN PDF预览

ADM705AN

更新时间： 2024-02-15 17:30:15
品牌 Logo 应用领域
亚德诺 - ADI 电源电路电源管理电路光电二极管监控输入元件
页数 文件大小 规格书
8页 144K
描述
Low Cost uP Supervisory Circuits

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ADM705AN 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：0.67
其他特性：RESET THRESHOLD VOLTAGE IS 4.65V; MANUAL RESET INPUT可调阈值：NO
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1信道数量：2
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Power Management Circuits
最大供电电流 (Isup)：0.25 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm
Base Number Matches：1

ADM705AN 数据手册

 浏览型号ADM705AN的Datasheet PDF文件第1页浏览型号ADM705AN的Datasheet PDF文件第2页浏览型号ADM705AN的Datasheet PDF文件第4页浏览型号ADM705AN的Datasheet PDF文件第5页浏览型号ADM705AN的Datasheet PDF文件第6页浏览型号ADM705AN的Datasheet PDF文件第7页 
ADM705–ADM708  
PIN FUNCTION DESCRIPTION  
Pin No.  
ADM707  
ADM708  
ADM705  
ADM706  
Mnemonic DIP, SOIC DIP, SPOC MicroSOIC  
Function  
MR  
1
1
3
Manual Reset Input. When taken below 0.8 V, a RESET is gener-  
ated. MR can be driven from TTL, CMOS logic or from a manual  
reset switch as it is internally debounced. An internal 250 µA pull-up  
current holds the input high when floating.  
VCC  
2
3
4
2
3
4
4
5
6
5 V Power Supply Input.  
GND  
PFI  
0 V. Ground reference for all signals.  
Power-Fail Input. PFI is the noninverting input to the Power-Fail  
Comparator. When PFI is less than 1.25 V, PFO goes low. If unused,  
PFI should be connected to GND or VCC  
.
PFO  
5
6
5
7
Power-Fail Output. PFO is the output from the Power-Fail Compara-  
tor. It goes low when PFI is less than 1.25 V.  
WDI  
N/A  
N/A  
Watchdog Input. WDI is a three-level input. If WDI remains either  
high or low for longer than the watchdog timeout period, the watch-  
dog output WDO goes low. The timer resets with each transition at  
the WDI input.  
Either a high-to-low or a low-to-high transition will clear the counter.  
The internal timer is also cleared whenever reset is asserted. The  
watchdog timer is disabled when WDI is left floating or connected to  
a three-state buffer.  
NC  
N/A  
7
6
7
8
1
No Connect.  
RESET  
Logic Output. RESET goes low for 200 ms when triggered. It can be  
triggered either by VCC being below the reset threshold or by a low  
signal on the manual reset (MR) input. RESET will remain low  
whenever VCC is below the reset threshold (4.65 V in ADM705, 4.4 V  
in ADM706). It remains low for 200 ms after VCC goes above the  
reset threshold or MR goes from low to high. A watchdog timeout  
will not trigger RESET unless WDO is connected to MR.  
WDO  
8
N/A  
N/A  
Logic Output. The Watchdog Output, WDO, goes low if the internal  
watchdog timer times out as a result of inactivity on the WDI input. It  
remains low until the watchdog timer is cleared. WDO also goes low  
during low line conditions. Whenever VCC is below the reset threshold,  
WDO remains low. As soon as VCC goes above the reset threshold,  
WDO goes high immediately.  
RESET  
N/A  
8
2
Logic Output. RESET is an active high output suitable for systems  
that use active high RESET logic. It is the inverse of RESET.  
PIN CONFIGURATION  
DIP, SOIC  
DIP, SOIC  
MicroSOIC  
RESET  
RESET  
MR  
1
2
3
4
8
7
6
5
NC  
1
2
3
4
8
1
2
3
4
MR  
WDO  
RESET  
WDI  
MR  
8
7
6
5
RESET  
RESET  
NC  
ADM707/  
ADM708  
PFO  
PFI  
ADM707/  
ADM708  
ADM705/  
ADM706  
V
7
6
5
V
CC  
CC  
TOP VIEW  
GND  
PFI  
TOP VIEW  
GND  
TOP VIEW  
(Not to Scale)  
(Not to Scale)  
(Not to Scale)  
V
GND  
CC  
PFO  
PFI  
PFO  
NC = NO CONNECT  
NC = NO CONNECT  
REV. B  
–3–  
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