ADM1485–SPECIFICATIONS
(VCC = 5 V ؎ 5%. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Min Typ Max
Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD
5.0
5.0
5.0
5.0
0.2
3
0.2
250
250
0.8
V
V
V
V
V
V
V
R = ∞, Test Circuit 1
2.0
1.5
1.5
VCC = 5 V, R = 50 Ω (RS-422), Test Circuit 1
R = 27 Ω (RS-485), Test Circuit 1
VTST = –7 V to +12 V, Test Circuit 2
R = 27 Ω or 50 Ω, Test Circuit 1
R = 27 Ω or 50 Ω, Test Circuit 1
R = 27 Ω or 50 Ω
VOD3
∆|VOD| for Complementary Output States
Common-Mode Output Voltage VOC
∆|VOD| for Complementary Output States
Output Short-Circuit Current (VOUT = High)
Output Short-Circuit Current (VOUT = Low)
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Input Current (DE, DI)
35
35
mA –7 V ≤ VO ≤ +12 V
mA –7 V ≤ VO ≤ +12 V
V
V
µA
2.0
1.0
RECEIVER
Differential Input Threshold Voltage, VTH
Input Voltage Hysteresis, ∆VTH
Input Resistance
–0.2
12
+0.2
V
–7 V ≤ VCM ≤ +12 V
70
mV VCM = 0 V
kΩ
mA
mA
V
V
µA
V
–7 V ≤ VCM ≤ +12 V
Input Current (A, B)
1
–0.8
0.8
V
V
IN = +12 V
IN = –7 V
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL
CMOS Output Voltage High, VOH
Short-Circuit Output Current
2.0
1
0.4
IOUT = +4.0 mA
IOUT = –4.0 mA
4.0
7
V
mA
85
VOUT = GND or VCC
Three-State Output Leakage Current
1.0
µA
0.4 V ≤ VOUT ≤ 2.4 V
POWER SUPPLY CURRENT
I
CC (Outputs Enabled)
1.0
0.6
2.2
1
mA Digital Inputs = GND or VCC
mA Digital Inputs = GND or VCC
ICC (Outputs Disabled)
Specifications subject to change without notice.
(V = 5 V ؎ 5%. All specifications TMIN to TMAX, unless otherwise noted.)
TIMING SPECIFICATIONS
CC
Parameter
Min Typ Max
Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output tPLH, tPHL
Driver O/P to O/P tSKEW
Driver Rise/Fall Time tR, tF
Driver Enable to Output Valid
Driver Disable Timing
2
10
1
8
10
10
0
15
5
15
25
25
2
ns
ns
ns
ns
ns
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
RL = 110 Ω, CL = 50 pF, Test Circuit 4
RL = 110 Ω, CL = 50 pF, Test Circuit 4
Matched Enable Switching
|tAZH –tBZL|, |tBZH –tAZL
RL = 110 Ω, CL = 50 pF, Test Circuit 4*
|
Matched Disable Switching
0
2
ns
RL = 110 Ω, CL = 50 pF, Test Circuit 4*
|tAHZ –tBLZ|, |tBHZ –tALZ
RECEIVER
|
Propagation Delay Input to Output tPLH, tPHL
8
15
30
5
20
20
ns
ns
ns
ns
ns
ns
CL = 15 pF, Test Circuit 5
CL = 15 pF, Test Circuit 5
CL = 15 pF, RL = 1 kΩ, Test Circuit 6
CL = 15 pF, RL = 1 kΩ, Test Circuit 6
Skew |tPLH –tPHL
|
Receiver Enable tEN1
Receiver Disable tEN2
Tx Pulse Width Distortion
Rx Pulse Width Distortion
5
5
1
1
*Guaranteed by characterization.
Specifications subject to change without notice.
–2–
REV. E